ISA-to-PC-Card (PCMCIA) Controllers
—
PD6710/
’
22
Datasheet
105
t
2a
IOCS16* inactive delay from SA[15:0]
1
40
ns
t
3
SA[16:0], SBHE* setup to any Command active
1, 2
LA[23:17] latching by ALE to any Command active
30
90
ns
ns
t
4
Any Command active to IOCHRDY inactive (low)
3
40
ns
t
4a
IOCHRDY three-state from Command inactive
4
5
30
t
5
MEMCS16* inactive delay from unlatched LA[23:17]
40
ns
t
6a
IOW* or IOR* pulse width
1
140
ns
t
6b
MEMW* or MEMR* pulse width
1
180
ns
t
7
Any Command inactive to next Command active
100
ns
t
8
Address or SBHE* hold from any Command inactive
0
ns
t
9
Data valid from MEMW* active
5
Data valid from IOW* active
40
40
ns
ns
t
10
Data hold from MEMW* inactive
Data hold from IOW* inactive
5
5
ns
ns
t
11
Data delay from IOR* active, for internal registers
0
130
ns
t
12
Data delay from IOCHRDY active
15
ns
t
13
Data hold from IOR* or MEMR* inactive
0
30
ns
t
14
AEN inactive setup to valid IOR* or IOW* active
40
ns
t
15
AEN hold from IOR* or IOW* inactive
5
ns
t
16
REFRESH* inactive setup to valid MEMR* or MEMW* active
40
ns
t
17
REFRESH* inactive hold from MEMR* or MEMW* active
0
ns
t
18
MEMCS16* active delay from SA[16:12] valid
40
ns
t
19
*ZWS delay from MEMW* active
30
ns
t
20
*ZWS hold from MEMW* inactive
15
ns
Table 26. ISA Bus Timing
(Sheet 2 of 2)
Symbol
Parameter
MIN
MAX
Unit
1. AEN must be inactive for t
, t
, and t
timing specifications to be applicable.
2. Command is defined as IOR*, IOW*, MEMR*, or MEMW*.
3. Except for valid card memory writes, which are zero wait state when internal write FIFO is not full.
4. If card is removed during a card access cycle, IOCHRDY is three-stated without waiting for end of Command.
5. Based on 25-MHz internal clock, produced either by an internal synthesizer and 14.318-MHz signal applied to CLK pin, or by
supplying 25 MHz directly to CLK pin and bypassing the internal synthesizer.