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參數(shù)資料
| 型號(hào)： | PD6710 |
| 廠商： | Intel Corp. |
| 英文描述： | ISA-to-PC-Card (PCMCIA) Controllers |
| 中文描述： | ISA -到- PC卡（PCMCIA）的控制器 |
| 文件頁(yè)數(shù)： | 35/138頁(yè) |
| 文件大?。?/td> | 723K |
| 代理商： | PD6710 |
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ISA-to-PC-Card (PCMCIA) Controllers
—
PD6710/
’
22
Datasheet
35
bit 5 is
‘
0
’
), system software can determine the card
’
s operating voltage range and then power-up
the socket and initialize the card (or simply initialize the card if programmed for automatic power-
on (
Power Control
register bit 5 is
‘
1
’
and
Extension Control 1
register bit 1 is
‘
1
’
)).
4.1.10
Write FIFO
To increase performance when writing to PC Cards, two, independent, four-word-deep write
FIFOs are used. Writes to PC Cards will complete without wait states until the FIFO is full.
Register states should not be changed until the write FIFO is empty.
4.1.11
Bus Sizing
The PD67XX incorporates logic to automatically detect its connection to 8- or 16-bit buses. This is
accomplished by sensing SBHE* input activity. If the SBHE* pin is always high (that is, tied to
ISA_VCC), the PD67XX operates in 8-bit mode where all transfers occur on the lower data bus,
bits 7:0. Any occurrence of the SBHE* going low triggers the PD67XX to operate thereafter as a
16-bit device. 16-bit operation of the PD67XX is properly triggered when the SBHE* input is
connected to the system
’
s SBHE* signal. When the PD67XX is operating in 16-bit mode, all ISA
bus transactions are 16-bit whenever possible, even if installed PC cards only support 8-bit
transfers. In 16-bit mode, the signals SBHE* and SA0 are used to specify the width of the data
transfer and the location of data on the bus (which byte lane has the data) during 8-bit transfers.
The possible combinations for SBHE* and SA0 are shown in
Table 9
and
Table 10
.
Typically, there are three types of data transfers to and from the PD67XX:
16-Bit Transfer from 16-Bit Processor —
The CPU puts the address on the bus. Then the
PD67XX identifies the address on the bus as either an 8- or 16-bit transfer. If the transfer is
identified as 16-bit, the host acknowledges with the appropriate signal, either MEMCS16* or
IOCS16*. Data is transferred to/from the data bus as a word on both byte lanes.
8-Bit Transfer from 16-Bit Processor
—
The CPU puts the address on the bus. Then the
PD67XX identifies the address on the bus as either an 8- or 16-bit transfer. In this case, the
transfer is identified as an 8-bit transfer. The host queries SA0 and SBHE* to determine the
Table 9. 16-Bit Mode Operation
16-Bit Mode Transfer Types
SBHE*
SA0
Word
0
0
Upper Byte/Odd Address
0
1
Low Byte/Even Address
1
0
Not Valid
1
1
Table 10. 8-Bit Mode Operation
8-Bit Mode Transfer Types
1
SA0
Even Address
0
Odd Address
1
1. The SBHE* signal is pulled up. If the SBHE*
signal remains high, thePD67XX causes all
transfers to occur on D[7:0] only
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