參數(shù)資料
型號: PD6710
廠商: Intel Corp.
英文描述: ISA-to-PC-Card (PCMCIA) Controllers
中文描述: ISA -到- PC卡(PCMCIA)的控制器
文件頁數(shù): 111/138頁
文件大小: 723K
代理商: PD6710
ISA-to-PC-Card (PCMCIA) Controllers
PD6710/
22
Datasheet
111
16.4.5.1
PC Card Socket Timing
Table 31. Memory Read/Write Timing (Word Access)
Symbol
Parameter
MIN
MAX
Units
t
1
-CE[2:1], -REG, Address, and Write Data setup to Command
active
1
(S
×
Tcp)
10
ns
t
2
Command pulse width
2
(C
×
Tcp)
10
ns
t
3
Address hold and Write Data valid from Command inactive
3
(R
×
Tcp)
10
ns
t
4
-WAIT active from Command active
4
(C
2)Tcp
10
ns
t
5
Command hold from -WAIT inactive
(2 Tcp) + 10
ns
t
6
Data valid from -WAIT inactive
Tcp + 10
ns
t
7
Data setup before -OE inactive
(2 Tcp) + 10
ns
t
8
Data hold after -OE inactive
0
ns
1. The Setup time is determined by the value programmed into the
Setup Timing
register, index 3Ah/3Dh. Using the Timer Set
0 default value of 01h, the setup time would be 70 ns. S = (N
pres
×
N
val
+ 1), see
PC Card Bus Timing Calculations
on
page 109
.
2. The Command time is determined by the value programmed into the
Command Timing
register, index 3Bh/3Eh. Using the
Timer Set 0 default value of 06h, the Command time would be 270 ns. C = (N
×
N
val
+ 1), see page
109
.
3. The Recovery time is determined by the value programmed into the
Recovery Timing
register, index 3Ch/3Fh. Using the
Timer Set 0 default value of 03h, the hold (Recovery) time would be 150 ns. R = (N
×
N
+ 1), see page
109
.
4. For typical active timing programmed at 280 ns, maximum -WAIT timing is 190 ns after Command active.
Figure 23. Memory Read/Write Timing
-REG, -CE[2:1],
t
1
t
2
t
4
t
3
-WAIT
t
7
D[15:0]
D[15:0]
t
8
t
5
A[25:0]
-OE, -WE
t
6
Write Cycle
Read Cycle
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