參數(shù)資料
型號： P95020ZLLG
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 電源管理
英文描述： 2-CHANNEL POWER SUPPLY MANAGEMENT CKT, PBGA124
封裝： LLGA-124
文件頁數(shù)： 97/137頁
文件大?。?/td> 3533K
代理商： P95020ZLLG
P95020 / Preliminary Datasheet
Revision 0.7.10
62
2010 Integrated Device Technology, Inc.
TCXO_IN: 12 MHz, 13 MHz, 19.2 MHz or 26 MHz TXCO Clock Input
047
VDD_CKGEN33
Internal 3.3V CKGEN LDO. Connect filter capacitor from this pin to CKGEN_GND
048
HXTALIN/TCXO_OUT1
HXTALIN: 12 MHz, 13 MHz, 19.2 MHz or 26 MHz Crystal Oscillator Input
TCXO_OUT1: Buffered TXCO_IN/HXTAL Clock Output #1, 32.768 kHz Output, 24 MHz PLL Output
049
TCXO_OUT2
Buffered TXCO_IN/HXTAL Clock Output #2, 12 MHz PLL Output, 48 MHz PLL Output
050
SYS_CLKOUT
12 MHz Output or Buffered Output of TCXO_IN/HXTAL
051
CKGEN_GND
PLL Analog Ground
052
USB_CLKOUT
24 MHz or 48 MHz Output
053
VDDIO_CK
Power Supply Input for TCXO_OUT1 and TCXO_OUT2 (1.1V
– 1.9V)
4.2
CKGEN - OSCILLATOR CIRCUIT ELECTRICAL CHARACTERISTICS
Unless otherwise specified, typical values at TA =25C, VDD_CKGEN33 = 3.3V, VDD_CKGEN18 = 1.8V, VSYS = 3.8V, TA = -40°C to +85°C,
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
VDD_CKGEN33
Operating Voltage
Internal LDO Regulator
2.97
3.3
3.63
V
VDD_CKGEN18
Internal LDO Regulator
1.62
1.8
1.98
V
VDDIO_CK
Power Input for TCXO_OUT1 and
TCXO_OUT2
1.1
1.9
V
IDD_CKGEN33
Supply Current
4
mA
IDD_CKGEN18
1
mA
VDDIO_CK
2
mA
VIH
TCXO_IN High Level Input
Voltage
0.7xVDD_
CKGEN18
VDD_CKG
EN18 +
0.3
V
VIL
TCXO_IN Low Level Input
Voltage
-0.3
0.3xVDD_
CKGEN18
V
VIH
32KHZ_CLKIN High Level Input
Voltage
0.7x
VLD0_LP
VLD0_LP +
0.3
V
VIL
32KHZ_CLKIN Low Level Input
Voltage
-0.3
0.3x
VLD0_LP
V
VOH
Output High for SYS_CLK,
USB_CLK
IOH = -4mA
0.7xVDD_
CKGEN33
V
VOL
Output Low for SYS_CLK,
USB_CLK
IOL = 4mA
0.3xVDD_
CKGEN33
V
VOH
Output High for 32KHZ_OUT2
IOH = -1mA
0.7xVDD_
CKGEN33
V
VOL
Output Low for 32KHZ_OUT2
IOL = 1mA
0.3xVDD_
CKGEN33
V
VOH
Output High for TCXO_OUT
VDDIO_CK = 1.8V, IOH = -4mA
0.7xVDDI
O_CK
V
VOL
Output Low for TCXO_OUT
VDDIO_CK = 1.8V, IOL = 4mA
0.3xVDDI
O_CK
V
VOH
Output High for TCXO_OUT
VDDIO_CK = 1.2V, IOH = -1mA
0.7xVDDI
O_CK
V
VOL
Output Low for TCXO_OUT
VDDIO_CK = 1.2V, IOL = 1mA
0.3xVDDI
O_CK
V
fo_CLK32
Input Frequency
32 kHz Clock
32.768
kHz
fo_CLKTCXO
Input Frequency
TCXO_IN
12MHZ, 13MHZ, 19.2MHZ,
26MHZ
ESRCLK32
Series Resistance
45
k
CL_CLK32
Load Capacitance
6
pF
tOR/tOF
Output Rise Time/Fall Time
32 kHz output, Note 1
Between 20% to 80%,
5.0
ns
tOR/tOF
Output Rise Time/Fall Time
SYS_CLK, USB_CLK output,
Note 3
Between 20% to 80%,
1.2
ns
tOR/tOF
Output Rise Time/Fall Time
Other outputs, Note 1
Between 20% to 80%,
1.8
ns
tSKEW
Output-Output Skew
TCXO_1 to TXCO_2
±50
ps
IOS
Short Circuit Current
Clock outputs
±70
mA
RO
Output Impedance
20
DCLOCKOUT
Output Clock Duty Cycle,
Oscillator Buffered Output
40
60
%
DCLOCKOUT
Output Clock Duty Cycle, PLL
Output
45
55
%
FSYN-ERR
Frequency Synthesis Error
0
ppm
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