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| 型號(hào)： | P95020ZLLG |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 電源管理 |
| 英文描述： | 2-CHANNEL POWER SUPPLY MANAGEMENT CKT, PBGA124 |
| 封裝： | LLGA-124 |
| 文件頁(yè)數(shù)： | 13/137頁(yè) |
| 文件大小： | 3533K |
| 代理商： | P95020ZLLG |
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P95020 / Preliminary Datasheet
Revision 0.7.10
11
2010 Integrated Device Technology, Inc.
MODULE
PIN #
PIN NAME
DESCRIPTION
I/O TYPE
CHARGER
102
CHRG_GND1
Pins 102 & 103 are the Power GND Pins for the Switching Regulator in the
Charger. Due to their higher current requirement they are internally tied
together & must be connected externally at the PC board also.
A-I
103
CHRG_GND2
A-I
104
CHRG_SW1
Pins 104 and 105 connect to the inductor of the switch-mode step-down
regulator for the Battery Charger. Due to their higher current requirement
they are internally tied together & must be connected externally at the PC
board also.
A-O
105
CHRG_SW2
A-O
106
CHRG_INPUT1
Pins 106 and 107 provide 5V VBUS Input Power from the USB or from an
external wall mounted external supply. Due to their higher current
requirement they are internally tied together & must be connected externally
at the PC board also.
AP-I
107
CHRG_INPUT2
AP-I
108
CHRG_SYSVCC1
Pins 108 and 109 are System VCC Output (VSYS). Due to their higher
current requirement they are internally tied together & must be connected
externally at the PC board also.
A-O
109
CHRG_SYSVCC2
A-O
110
CHRG_BAT1
Pins 110 and 111 form the positive battery lead connection to a single cell Li-
Ion/Li-Poly battery. Due to their higher current requirement they are internally
tied together & must be connected externally at the PC board also.
AP-I/O
111
CHRG_BAT2
AP-I/O
112
CHRG_CLSEN
Input Current Limit Sense/filtering pin for current limit detection
A-I
113
CHRG_ICHRG
Current setting. Connect to a current sense resistor
AP-I/O
114
CHRG_GATE
Gate Drive for (Optional) External Ideal Diode
A-O
115
CHRG_NTC
Thermal Sense, Connect to
a batterys thermistor
A-I
116
CHRG_VNTC
NTC Power output. This pin provides power to the NTC resistor string.
AP-O
This output is automatically CHRG_SYSVCC level but only enabled when
NTC measurement is necessary to save power.
GPIO_TSC
117
GND_BAT/ADCGND
GND_BAT & ADCGND: Shared analog ground pin for battery charger and
ADC.
GND
(See Pins
118
DGND
Digital Ground
GND
001-006
119
POR_OUT
Power-On-Reset Output, Active Low
GPIO-OUT
also)
120
SW_DET
Switch Detect Input
GPIO
121
GPIO1/SW_OUT/PENDOWN
GPIO 1: General Purpose I/O # 1
GPIO
SW_OUT: Switch Detect Output
PENDOWN: PENDOWN Detect Output
122
GPIO2/LED1
GPIO 2: General Purpose I/O # 2
GPIO
LED1: Charger LED # 1 Indicates charging in progress
123
GPIO3/LED2
GPIO 3: General Purpose I/O # 3
GPIO
LED2: Charger LED # 2 Indicates charging complete
124
GPIO4/CHRG_ILIM
GPIO 4: General Purpose I/O # 4
GPIO
CHRG_ILIM: Control the current limit of the Charger Pre-Regulator.
CHRG_ILIM = 0, limit current to 500mA; CHRG_ILIM = 1, limit current to
1.5A
Table 2 - NQG132 Pin Functions by Pin Number (see Figure 3)
MODULE
PIN #
PIN NAME
DESCRIPTION
I/O TYPE
GPIO_TSC
(See Pins
B57
– A71
also)
A1
GPIO5/INT_OUT
GPIO 5: General Purpose I/O # 5
GPIO
INT_OUT : Interrupt Output
A2
NC
No Connect
NC
B1
GPIO7/ADC3
GPIO 7: General Purpose I/O # 7
GPIO
ADC3 : Auxiliary Input Channel 4 / Y- pin to 4 wire resistive touch screen
A3
GPIO6/ADC1
GPIO 6: General Purpose I/O # 6
GPIO
ADC1 : Auxiliary Input Channel 2 / X- pin to 4-wire resistive touch screen
B2
GPIO8/ADC2
GPIO 8: General Purpose I/O # 8
GPIO
ADC2 : Auxiliary Input Channel 3 / Y+ pin to 4-wire resistive touch screen
A4
GPIO9/ADC0/MCLK_IN
GPIO 9: General Purpose I/O # 9
GPIO
ADC0 : Auxiliary Input Channel 1 / X+ pin to 4-wire resistive touch screen
MCLK_IN : Master Clock Input
B3
GPIO10
GPIO 10: General Purpose I/O # 10
GPIO
AUDIO
A5
MIC_R-
MIC_R-: Analog Microphone Differential Stereo Right Inverting Input
A-I
B4
MIC_R+/DMICDAT2
MIC_R+: Analog Microphone Differential Stereo Right Non-Inverting Input
A-I
DMICDAT2: Digital Microphone 2 Data Input
D-I
A6
MICBIAS_R/DMICSEL
MICBIAS : Microphone Right Bias
A-O
DMICSEL : Digital Microphone Select (Common to both inputs)
D-O
B5
MICBIAS_L/DMICCLK
MICBIAS : Microphone Left Bias
A-O
DMICCLK : Digital Microphone Clock (Common to both inputs)
D-O
A7
MIC_L+/DMICDAT1
MIC_L+ : Analog Microphone Differential Stereo Left Non-Inverting Input
A-I
DMICDAT1 : Digital Microphone 1 Data Input
D-I
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