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| 型號(hào)： | P95020ZLLG |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類(lèi)： | 電源管理 |
| 英文描述： | 2-CHANNEL POWER SUPPLY MANAGEMENT CKT, PBGA124 |
| 封裝： | LLGA-124 |
| 文件頁(yè)數(shù)： | 20/137頁(yè) |
| 文件大?。?/td> | 3533K |
| 代理商： | P95020ZLLG |
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P95020 / Preliminary Datasheet
Revision 0.7.10
116
2010 Integrated Device Technology, Inc.
15.0 I2C_I2S MODULE
FEATURES
IC Master supports interface to external ROM
IC Slave supports interface to external IC Masters
400 kHz fast I2C protocol
Two IS interfaces
Access arbiter that arbitrates the access request from
I2C slave or embedded microcontroller
Interrupt handler which merge or re-direct the interrupts
from functional module to internal or external processor
DESCRIPTION
The P95020
s IC master port is intended for IC ROM
access only. The contents of an external ROM that are
attached to the IC Master port are automatically read into
an internal 1.5 kbyte shadow memory. The IC Master
port conforms to the 400 kHz fast IC bus protocol and
supports 7-bit device/page addressing.
The P95020
s IC Slave port follows I2C bus protocol
during register reads or writes that are initiated by an
external IC Master (typcially an application processor).
The IC Slave port operates at up to 400 kHz and
supports 7-bit device/page addressing.
The P95020 includes two IS interfaces that provide audio
inputs to the Audio Module described in Section 2.0.
15.1 I2C_I2S - PIN DEFINITIONS
Pin #
PIN_ID
DESCRIPTION
054
EX_ROM
ROM Select. EX_ROM = 1, read contents of external ROM into internal shadow memory. EX_ROM = 0, read contents
of internal ROM.
055
DGND
Digital Ground (1)
056
I2S_BCLK2
IS Bit Clock Channel 2
057
I2S_WS2
IS Word Select Channel 2
058
I2S_SDOUT2
IS Serial Data OUT Channel 2
059
I2S_SDIN2
IS Serial Data IN Channel 2
060
I2S_BCLK1
IS Bit Clock Channel 1
061
I2S_WS1
IS Word Select (Left/Right) Channel 1
062
I2S_SDOUT1
IS Serial Data OUT Channel 1
063
I2S_SDIN1
IS Serial Data IN Channel 1
064
I2CS_SCL
IC Slave clock
065
I2CS_SDA
IC Slave data
066
I2CM_SCL
IC Master clock
067
I2CM_SDA
IC Master data
068
GND
GND : Ground
15.2 IC SLAVE
15.2.1
The IC ports on the P95020 operate at a maximum speed of 400 kHz. The IC slave address that the P95020 responds
to is defined in the I2C_SLAVE_ADDR global register. The default IC device address after reset is 0101010, and can be
changed by firmware during the start up sequence.
The IC slave supports two interface timing modes: Non-Stretching and Stretching.
In Non-Stretching Mode, the IC slave does not stretch the input clock signal. The registers are pre-fetched to speed up
the read access in order to meet the 400 kHz speed. This is the default mode of operation and is intended for use with
IC masters that do not supporting clock stretching.
In Stretching Mode, the IC slave may stretch the clock signal (hold I2CS_SCL low) during the ACK / NAK phase (byte
level stretching) when the internal read access request is not finished. Stretching is not supported during write accesses.
15.2.2
IC Slave - Write/Read Operation
The configuration and status registers for the various functional blocks are mapped to 3 consecutive 256 byte pages. The
page ID is encoded to 0,1, and 2. The definition and mapping is defined in Table 3
on page 20. The first 16 bytes in any of the 3 pages map to the same set of global registers. The
“current active page” ID
for IC access is defined in the global page ID register.
The IC uses an 8-bit register address (Reg_addr in below) to define the register access start address in an IC access in
the current page. The register address can be programmed by writing the register value immediately after device
address. Subsequent write accesses will be directed to the register defined by the register address in the current active
page. Read accesses will return the register defined by the register address. The register address is incremented
automatically byte-per-byte during each read/write access.
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