- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄98050 > P95020ZLLG (INTEGRATED DEVICE TECHNOLOGY INC) 2-CHANNEL POWER SUPPLY MANAGEMENT CKT, PBGA124 PDF資料下載
參數(shù)資料
| 型號： | P95020ZLLG |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 電源管理 |
| 英文描述： | 2-CHANNEL POWER SUPPLY MANAGEMENT CKT, PBGA124 |
| 封裝： | LLGA-124 |
| 文件頁數(shù)： | 39/137頁 |
| 文件大?。?/td> | 3533K |
| 代理商： | P95020ZLLG |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁當(dāng)前第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁
P95020 / Preliminary Datasheet
Revision 0.7.10
133
2010 Integrated Device Technology, Inc.
18.0 APPLICATIONS INFORMATION
18.1 EXTERNAL COMPONENTS
The P95020 requires a minimum number of external components for proper operation.
18.2 DIGITAL LOGIC DECOUPLING CAPACITORS
As with any high-performance mixed-signal IC, the P95020 must be isolated from the system power supply noise to
perform optimally. A decoupling capacitor of 0.01
μF must be connected between each power supply and the PCB
ground plane as close to these pins as possible. For optimum device performance, the decoupling capacitor should be
mounted on the component side of the PCB. Avoid the use of vias in the decoupling circuit.
18.3 CLASS_D CONSIDERATIONS
The CLASS_D amplifier should have one 330uF and one 0.1uF capacitor to ground at its VDD pin.
The CLASS_D output also should have a series connected snubber consisting of a 5.1 ohm, 0603 resistor and a 220pF
capacitor across the speaker output pins. No other filtering is required.
The CLASS_D BTL plus and minus output traces must be routed side by side in pairs.
18.4 SERIES TERMINATION RESISTORS
Clock output traces over one inch should use series termi
nation. To series terminate a 50Ω trace (a commonly used trace
impedance), place a 33Ω resistor in series with the clock line, as close to the clock output pin as possible. The nominal
impedance of the clock output is 20Ω.
18.5 IC EXTERNAL RESISTOR CONNECTION
The SCK and SDATA pins can be connected to any voltage between 1.71 V and 3.6 V.
18.6 CRYSTAL LOAD CAPACITORS
To save discrete component cost, the P95020 integrates on-chip capacitance to support a crystal with CL=10 pF. It is
important to keep stray capacitance to a minimum by using very short PCB traces between the crystal and device. Avoid
the use of vias if possible.
18.7 PCB LAYOUT CONSIDERATIONS
For optimum device performance and lowest output phase noise, the following guidelines should be observed.
1.
The 0.01μF decoupling capacitors should be mounted on the component side of the board as close to the VDD pin as
possible. No vias should be used between the decoupling capacitors and VDD pins. The PCB trace to each VDD pin
should be kept as short as possible, as should the PCB trace to the ground via.
2.
The external crystal should be mounted just next to the device with short traces. The X1 and X2 traces should not be
routed next to each other with minimum spaces, instead they should be separated and away from other traces.
3.
To minimize EMI, the 33Ω series termination resistor (if needed) should be placed close to the clock output.
4.
An optimum layout is one with all components on the same side of the board, minimizing vias through other signal
layers. Other signal traces should be routed away from the P95020. This includes signal traces just underneath the
device, or on layers adjacent to the ground plane layer used by the device.
18.8 POWER DISSIPATION AND THERMAL REQUIREMENTS
The power dissipated in the P95020 will depend primarily
on the total internal power dissipation and the junction
temperature. Careful consideration must be given to the
overall thermal design. Actual thermal resistance
JA
must be determined at the customers end product level,
being based on the end package design parameters and
available device internal cooling. See Figure 37 for
required package power de-rating.
18.9 TYPICAL BLOCK PERFORMANCE
CHARACTERISTICS GRAPHS
This section is TBD.
110
100
90
80
70
60
50
40
30
20
10
120
-40
10
20
30
40
50
60
70
80
90 100 110 120 130
-30 -20 -10
0
R
at
ed
P
ow
er
(%
)
Junction Temperature (°C)
Figure 37 – Power Derating Curve (Typical)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| P95020ZLLGI | 2-CHANNEL POWER SUPPLY MANAGEMENT CKT, PBGA124 |
| P95020ZNQGI | 2-CHANNEL POWER SUPPLY MANAGEMENT CKT, QCC132 |
| P95020ZNQG | 2-CHANNEL POWER SUPPLY MANAGEMENT CKT, QCC132 |
| P95020ZLLG8 | 2-CHANNEL POWER SUPPLY MANAGEMENT CKT, PBGA124 |
| P95020ZLLGI8 | 2-CHANNEL POWER SUPPLY MANAGEMENT CKT, PBGA124 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| P95021NQG | 功能描述:PMIC 解決方案 Integrates Audio, LED B/Light Pwr Mgt RoHS:否 制造商:Texas Instruments 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-24 封裝:Reel |
| P95021NQG8 | 制造商:Integrated Device Technology Inc 功能描述:POWER MANAGEMENT, AUDIO & CONT 制造商:Integrated Device Technology Inc 功能描述:132-VFQFPN - Tape and Reel 制造商:Integrated Device Technology Inc 功能描述:Integrates Audio, LED B/Light Pwr Mgt |
| P950-36I | 制造商:Tripp Lite 功能描述:SERIAL ATA II SIGNAL CABLE, 2X7-PIN STRAIGHT CONNECTOR - 39" - Bulk |
| P9508- | 制造商:ROEBUCK 功能描述:ROEBUCK DISH WASHING BRUSH |
| P9-511121 | 功能描述:按鈕開關(guān) Flush Dome Solder 5A SPST-DB, SPDT-DB RoHS:否 制造商:OTTO 觸點形式: 開關(guān)功能: 電流額定值: 電壓額定值 AC: 電壓額定值 DC: 功率額定值: 安裝風(fēng)格: 照明: 照明顏色: IP 等級: 端接類型: 觸點電鍍: 執(zhí)行器: 蓋顏色: 封裝: 可燃性等級: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。