參數(shù)資料
型號(hào)： P95020ZLLG8
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 電源管理
英文描述： 2-CHANNEL POWER SUPPLY MANAGEMENT CKT, PBGA124
封裝： LLGA-124
文件頁數(shù)： 99/137頁
文件大?。?/td> 3533K
代理商： P95020ZLLG8
P95020 / Preliminary Datasheet
Revision 0.7.10
64
2010 Integrated Device Technology, Inc.
by crystal frequency drift caused by temperature shifts. External circuit noise coupled into the oscillator circuit may result
in the clock running fast. Pay attention to PC board layout for isolating the crystal and oscillator from noise.
4.7
CKGEN
– CLOCK GENERATOR REGISTERS
4.7.1
CKGEN
– CLOCK GENERATOR PLL CONFIGURATION REGISTER
IC Address = Page-0: 52(0x34), C Address = 0xA034
Bit
Bit Name
Def.
Set.
User
Type
Value
Description / Comments
[2:0]
S2/S1/SO
000b
R/W
000b = PLL off
001b = PLL on, 26MHz
TCXO_IN as reference clock
010b = PLL on, 32kHz
XTAL_IN as reference clock
011b = PLL on, 26MHz
TCXO_IN as reference clock
100b = PLL off
101 = PLL on, 12MHz
TCXO_IN is reference clock
110b = PLL on, 13 MHz
TCXO_IN is reference clock
111b = PLL on, 19.2 MHz
TCXO_IN is reference clock
3
CLK2M_RATE
0b
R/W
0b = 2 MHz
1b = 1 MHz
Tuch Screen Controller Clock
4
SSC_DELTA
0b
R/W
0b = +/- 1%
1b= +/- 2%
SSC frequency offset setting
5
SSC_EN
0b
R/W
0b = Disabled
1b = Enabled
DCDC 24MHz clock SSC enable
6
SYS_CLK_OUT_EN 1b
R/W
0b = Disabled
1b = Enabled
SYS_CLK clock output enabled
7
USB_CLK_OUT_EN 1b
R/W
0b = Disabled
1b = Enabled
USB_CLK clock output enable
4.7.2
CKGEN
– PLL STATUS REGISTER
IC Address = Page-0: 53(0x35), C Address = 0xA035
Bit
Bit Name
Def.
Set.
User
Type
Value
Description / Comments
0
PLL_LOCK1
0b
R
0b = Not locked
1b = Locked
Main PLL lock status
1
TCXO1_EN
0b
R/W
0b = Disabled
1b = Enabled
TCXO #1 enable
2
TCXO2_EN
0b
R/W
0b = Disabled
1b = Enabled
TCXO #2 enable
3
RESERVED
0b
R/W
RESERVED
4
32KOUT1_EN
0b
R/W
0b = Disabled
1b = Enabled
32K clock #1 enable
5
32KOUT2_EN
0b
R/W
0b = Disabled
1b = Enabled
32K clock #2 enable
6
32K_STABLE
0b
R
0b = Unstable
1b = Stable
32K oscillator or input stable
7
RESERVED
0b
R
RESERVED
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