參數(shù)資料
型號： P95020ZLLG8
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 電源管理
英文描述： 2-CHANNEL POWER SUPPLY MANAGEMENT CKT, PBGA124
封裝： LLGA-124
文件頁數(shù)： 117/137頁
文件大?。?/td> 3533K
代理商： P95020ZLLG8
P95020 / Preliminary Datasheet
Revision 0.7.10
80
2010 Integrated Device Technology, Inc.
Bit
Setting
Output
Voltage
Bit
Setting
Output
Voltage
Bit
Setting
Output
Voltage
Bit
Setting
Output
Voltage
Bit
Setting
Output
Voltage
0010000
1.150
0101000
1.750
1000000
2.350
1011000
2.950
1110000
3.550
0010001
1.175
0101001
1.775
1000001
2.375
1011001
2.975
1110001
3.575
0010010
1.200
0101010
1.800
1000010
2.400
1011010
3.000
1110010
3.600
0010011
1.225
0101011
1.825
1000011
2.425
1011011
3.025
1110011
3.625
0010100
1.250
0101100
1.850
1000100
2.450
1011100
3.050
1110100
3.650
0010101
1.275
0101101
1.875
1000101
2.475
1011101
3.075
1110101
3.675
0010110
1.300
0101110
1.900
1000110
2.500
1011110
3.100
1110110
3.700
0010111
1.325
0101111
1.925
1000111
2.525
1011111
3.125
Note
– Contains an initial 0.75V offset. Performance and accuracy are not guaranteed with bit combinations above 1110110.
8.4.2
BUCK1000 & BUCK500 - Control Register: (See Table 18 for addresses)
The Control Register contains the Current Limit setting bits, Control bits and Status bits.
Bit
Bit Name
Def.
Set.
User
Type
Value
Description / Comments
0
PWM_PFM
0
RW
1 = PFM mode
0 = PWM mode
PWM/PFM Mode Select
1
CLK_SEL
1
RW
1 = 2 MHz
0 = 1 MHz
Clock Frequency
[3:2]
I_LIM
3h
RW
Cycle by Cycle Current Limit (%)
4
SC_FAULT
N/A
R
1 = Fault
0 = OK
Short Circuit Fault
5
PGOOD
N/A
R
1 = Power Good
0 = Power Not
Good
Power Good
6
RESERVED
1b
RW
RESERVED
7
DAC_MSB_EN
1b
RW
1 = Enable writes to
BUCK 3 MSB bits in
DAC
0 = Disable writes to
BUCK 3 MSB bits in
DAC
BUCK VOUT 3 MSB bits write protection
Table 20
– Control Register Cycle by Cycle Current Limit (I_LIM) Settings
for Bits [3:2] [Note ]
Bit 3
Bit
2
Description
0
Current Limit = 25 %
0
1
Current Limit = 50 %
1
0
Current Limit = 75 %
1
Current Limit = 100 %
Note
– Current Limit is at maximum when bits [3:2] are both set to 1.
8.5
BUCK1000 & BUCK500 - ENABLING & DISABLING
There are two methods of disabling each Buck Converter: the Global Enable bit and the local ENABLE bit (Output Voltage
Register, Bit 7). Table 21 shows the interoperation of the two methods.
Table 21
– Interoperability of enabling/disabling methods vs. loading default values.
Internal POR
Global Enable
ENABLE
ON/OFF status
REGISTER VALUE STATUS
0
X
0
OFF
PREVIOUS SETTINGS
0
X
OFF
PREVIOUS SETTINGS
0
1
ON
PREVIOUS SETTINGS
1
X
OFF
LOAD DEFAULT VALUES
8.5.1
BUCK1000 & BUCK500 - Initialization and Power-Up
During an IC re-
initialization or “cold boot” an internal POR disables the Buck Converter and loads the default values into
the registers. The default values are only loaded into the registers when there is a POR event.
The default settings for the Output Voltage Register are:
Function
Default Setting
Local Enable Bit
Disabled
Output Voltage
3.3V (BUCK500_0)
1.8V (BUCK500_1)
1.2V (BUCK1000)
The default settings for the Control Register are:
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