參數(shù)資料
型號(hào)： P95020ZLLG8
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 電源管理
英文描述： 2-CHANNEL POWER SUPPLY MANAGEMENT CKT, PBGA124
封裝： LLGA-124
文件頁數(shù)： 58/137頁
文件大?。?/td> 3533K
代理商： P95020ZLLG8
P95020 / Preliminary Datasheet
Revision 0.7.10
27
2010 Integrated Device Technology, Inc.
DMICDAT1
OR
DMICDAT2
DMICCLK
Right
Channel
Left
Channel
Valid
Data R
Valid
Data L
Valid
Data R
Valid
Data L
Valid
Data R
Digital
Microphones
DMICCLK
M
U
X
Stereo Channels
Output
Pin
On-Chip
Multiplexer
On-Chip
Off-Chip
STEREO
ADC1
DMICDAT1
OR
DMICDAT2
Shared
Data Input
Figure 7
–Stereo Digital Microphone (Mode 1 & 2)
2.5 AUDIO - ANALOG LINE INPUT
The Analog Line Input path consists of a stereo differential input analog buffer that is routed to the analog mixer and
ADC0. By using the analog mixer, the analog line input may be routed to ADC0, the line output port or the headphone
output port.
2.6 AUDIO - DAC, ADC
There are 2 stereo DACs and 2 stereo ADCs. All converters support sample rates of 8kHz, 11.025khz, 12kHz,
22.050kHz, 16kHz, 24kHz, 44.1kHz, 48kHz, 88.2kHz, and 96kHz. Word lengths of 16, 20 and 24-bits are selectable.
2.6.1
AUDIO - DAC 0/1
The DAC sample rate and word length are programmed at the IS input port and the DAC may select either IS port as the
data source.
Digital volume control provides -95.25 dB to 0dB gain in 0.75 dB steps and mute. The output of DAC0 and DAC1 is sent
to the analog mixer, the headphone output and the line output.
2.6.2
AUDIO - ADC 0/1
Each ADC includes a high pass filter to remove DC offsets present in the input path. Sample rate, word length, and
source ADC are programmed at the IS output port. If an ADC is selected as the data source for more than one sink (IS
output or DAC) then the rates must be programmed the same at all sinks. If the rates are not identical, then the highest
priority sink will dominate (I2Sout1, I2Sout2, and DAC). The other sink will be muted under these circumstances. ADC0
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