參數(shù)資料
型號(hào)： P95020ZLLG8
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 電源管理
英文描述： 2-CHANNEL POWER SUPPLY MANAGEMENT CKT, PBGA124
封裝： LLGA-124
文件頁(yè)數(shù)： 12/137頁(yè)
文件大小： 3533K
代理商： P95020ZLLG8
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P95020 / Preliminary Datasheet
Revision 0.7.10
109
2010 Integrated Device Technology, Inc.
Bit
Bit Name
Def.
Set.
User
Type
Value
Description / Comments
0
RESERVED
0b
R/W
RESERVED
[10:1]
GPIO_DAT
0000000000b
R/W
Pins configured as an output will reflect the value held in the
GPIO_DAT register. The GPIO_DAT register will follow the logic
level at the pin for pins configured as a level sentitive inputs. The
GPIO_DAT register will change from a 0 to a 1 when the input
transitions state from low to high (rising edge) or high to low
(falling edge) as determined by the GPIO INPUT EDGE SELECT
register for pins configured as level sensitive inputs.
[15:11]
RESERVED
R/W
RESERVED
13.7.3
GPIO INPUT MODE SELECT REGISTER
IC Address = Page-0: 36(0x24), C Address = 0xA024
IC Address = Page-0: 37(0x25), C Address = 0xA025
Bit
Bit Name
Def.
Set.
User
Type
Value
Description / Comments
0
RESERVED
0b
R/W
RESERVED
[10:1]
GPIO_IN_MODE
0000000000b
R/W
0 = Level
sensitive
1 = Edge
sensitive
0 = Level sensitive, GPIO_DAT reflects the input data for the
corresponding GPIO; 1 = Edge sensitive, rising/falling edges
trigger interrupts as defined in GPIO_IN_EDGE. Requires the
associated bit in the GPIO Direction Register to be set as an
input.
[15:11]
RESERVED
R/W
RESERVED
13.7.4
GPIO INTERRUPT ENABLE REGISTER
IC Address = Page-0: 38(0x26), C Address = 0xA026
IC Address = Page-0: 39(0x27), C Address = 0xA027
Bit
Bit Name
Def.
Set.
User
Type
Value
Description / Comments
0
RESERVED
0b
R/W
RESERVED
[10:1]
GPIO_INT_EN
0000000000b
R/W
0 = Interrupt
Disabled
1 = Interrupt
Enabled
Each bit enabled/disables the corresponding GPIO interrupt
[15:11]
RESERVED
R/W
RESERVED
13.7.5
GPIO INPUT EDGE REGISTER
IC Address = Page-0: 40(0x28), C Address = 0xA028
IC Address = Page-0: 41(0x29), C Address = 0xA029
Bit
Bit Name
Def.
Set.
User
Type
Value
Description / Comments
0
RESERVED
0b
R/W
RESERVED
[10:1]
GPIO_IN_EDGE
1111111111b
R/W
0 = Rising edge
trigger
1 = Rising and
falling edge trigger
0 = Rising edge generates interrupt. 1 = Rising edge and
falling edge generates interrupt.
[15:11]
RESERVED
R/W
RESERVED
13.7.6
GPIO INTERRUPT STATUS REGISTER
IC Address = Page-0: 42(0x2A), C Address = 0xA02A
IC Address = Page-0: 43(0x2B), C Address = 0xA02B
Bit
Bit Name
Def.
Set.
User
Type
Value
Description / Comments
0
RESERVED
0b
R/W
RESERVED
[10:1]
GPIO_INT_STATUS
0000000000b
RW1C
0 = No interrupt
1 = Interrupt
Event is defined by GPIO_IN_EDGE register
[15:11]
RESERVED
R/W
RESERVED
13.7.7
GPIO OUTPUT MODE REGISTER
IC Address = Page-0: 44(0x2C), C Address = 0xA02C
IC Address = Page-0: 45(0x2D), C Address = 0xA02D
Bit
Bit Name
Def.
Set.
User
Type
Value
Description / Comments
0
RESERVED
0b
R/W
RESERVED
[10:1]
GPIO_OUT_MODE
1111111111b
R/W
0 = CMOS output
1 = Open drain output
Sets the output mode for each corresponding GPIO
[15:11]
RESERVED
R/W
RESERVED
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