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| 型號(hào)： | P95020ZLLG8 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 電源管理 |
| 英文描述： | 2-CHANNEL POWER SUPPLY MANAGEMENT CKT, PBGA124 |
| 封裝： | LLGA-124 |
| 文件頁(yè)數(shù)： | 78/137頁(yè) |
| 文件大?。?/td> | 3533K |
| 代理商： | P95020ZLLG8 |
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P95020 / Preliminary Datasheet
Revision 0.7.10
45
2010 Integrated Device Technology, Inc.
2.15.16 AUDIO - Microphone Port Mode Control
Microphone mode selection and other microphone port related control.
The digital and analog port pins are shared. Analog or digital microphone mode is selected using this register. When in
digital mode, the DMICCLK, DMICDAT1, DMICDAT2 and DMICCSEL functions are available. When in analog mode, the
MIC_R+, MIC_R-, MIC_L+, MIC_L-, MICBIAS_R, MICBIAS_L are available.
The left and right outputs of ADC1 may be swapped using the L/R swap flag and mono output may be forced using the
mono flag. By using the L/R swap and mono flags together it is possible to support stereo capture, mono capture from the
left channel and mono capture from the right channel. When used in conjunction with the power management controls, it
is possible to shut down half of the ADC and still provide valid data on both the left and right digital output streams from
ADC1.
MIC_MODE = IC Address = Page-1: 184(0xB8), C Address = 0xA1B8, Offset = 0xB8
Bit
Bit Name
Def.
Set.
User
Type
Value
Description / Comments
0
AORD
0b
RW
0 = Analog MIC Mode
1 = Digital MIC Mode
Microphone Mode
1
LR_SWAP
0b
RW
0 = Dont Swap
1 = Swap
L/R Swap - swap left and right ADC1 channels
2
MONO
0b
RW
0 = Normal
1 = Left Copied to Right
Mono - Left channel is copied to right (implemented after L/R swap)
3
BIT_INVERT
0b
RW
0 = Dont Invert
1 = Invert
Bit invert - Input 1 as 0 and 0 as 1
[6:4]
RESERVED
000b
RW
RESERVED
7
AMIC_PWD
1b
RW
0 = Dont Power Down
1 = Power Down
Dedicated Analog Microphone Power Down
2.15.17 AUDIO - Analog Microphone Boost Gain Control Register
This register selects the amount of gain applied to the analog microphone before the ADC.
AMIC_BOOST = IC Address = Page-1: 185(0xB9), C Address = 0xA1B9, Offset = 0xB9
Bit
Bit Name
Def.
Set.
User
Type
Value
Description / Comments
[1:0]
AMBR
00b
RW
00b = 0 dB Gain
01b = 10 dB Gain
10b = 20 dB Gain
11b = 30 dB Gain
Right Boost
[3:2]
RESERVED
00b
RW
RESERVED
[5:4]
AMBL
00b
RW
00b = 0 dB Gain
01b = 10 dB Gain
10b = 20 dB Gain
11b = 30 dB Gain
Left Boost
[7:6]
RESERVED
00b
RW
RESERVED
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