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參數(shù)資料
| 型號： | P95020ZLLG8 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 電源管理 |
| 英文描述： | 2-CHANNEL POWER SUPPLY MANAGEMENT CKT, PBGA124 |
| 封裝： | LLGA-124 |
| 文件頁數(shù)： | 76/137頁 |
| 文件大小： | 3533K |
| 代理商： | P95020ZLLG8 |
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P95020 / Preliminary Datasheet
Revision 0.7.10
43
2010 Integrated Device Technology, Inc.
AMICR_MIX_VOL = IC Address = Page-1: 175(0xAF), C Address = 0xA1AF
Bit
Bit Name
Def.
Set.
User
Type
Value
Description / Comments
[4:0]
MMVR
0Ch
RW
00h = 12 dB gain
0Ch = 0 dB gain
1Fh = 34.5 dB attenuation
Right Volume Control
[6:5]
RESERVED
00b
RW
RESERVED
7
MUTE_R
1b
RW
0 = Not Muted
1 = Muted
Right Mute
2.15.10 AUDIO - ADC0 Analog Input Gain (Volume Control) Registers (ADC0x_IN_AGAIN)
These registers manage the input signal volume for ADC0, Left and Right respectively.
The MSB, bit D7, of each register is the mute bit. When this bit is set, the output of the gain stage is silent. Muting the
amplifier does not stop the ADC capture stream.
There are 16 gain selections from 22.5 dB to 0 dB. The step size is 1.5 dB.
ADC0L_IN_AGAIN = IC Address = Page-1: 176(0xB0), C Address = 0xA1B0
Bit
Bit Name
Def.
Set.
User
Type
Value
Description / Comments
[3:0]
A0VL
0h
RW
0h = 0 dB gain
Fh = 22.5 dB gain
Left Analog Input Gain Control
[6:4]
RESERVED
000b
RW
RESERVED
7
MUTE_L
1b
RW
0 = Not Muted
1 = Muted
Left Mute
ADC0R_IN_AGAIN = IC Address = Page-1: 177(0xB1), C Address = 0xA1B1
Bit
Bit Name
Def.
Set.
User
Type
Value
Description / Comments
[3:0]
A0VR
0h
RW
0h = 0dB gain
Fh = 22.5 dB gain
Right Analog Input Gain Control
[6:4]
RESERVED
000b
RW
RESERVED
7
MUTE_R
1b
RW
0 = Not Muted
1 = Muted
Right Mute
2.15.11 AUDIO - ADC0 Analog Input Selection Register (ADC0_MUX)
This register selects the input source for ADC0. ADC0 my record the line input or the mixer output.
ADC0_MUX = IC Address = Page-1: 178(0xB2), C Address = 0xA1B2
Bit
Bit Name
Def.
Set.
User
Type
Value
Description / Comments
0
A0LSEL0
0b
RW
0=Line Input
1=Mixer Iutput
Left Analog Input Select
[3:1]
RESERVED
000b
RW
RESERVED
4
A0RSEL0
0b
RW
0=Line Input
1=Mixer Iutput
Right Analog Input Select
[7:5]
RESERVED
000b
RW
RESERVED
2.15.12 AUDIO - ADC0 Control Register (ADC0_CTRL)
This register controls the functionality of the high pass filter for ADC0.
ADC0_CTRL = IC Address = Page-1: 179(0xB3), C Address = 0xA1B3
Bit
Bit Name
Def.
Set.
User
Type
Value
Description / Comments
[3:0]
RESERVED
0000b
RW
RESERVED
4
HPF_FREZ
0b
RW
0 = Disabled
1 = Enabled
High-pass filter freeze
5
RESERVED
0b
RW
RESERVED
6
HPF_DIS
0b
RW
0 = Not Disabled
1 = Disabled
High Pass Filter Disable
7
RESERVED
0b
RW
RESERVED
2.15.13 AUDIO - ADC1 Digital Input Gain Register (ADC1x_IN_DGAIN)
These registers manage the signal output volume for ADC1, Left and Right respectively.
The MSB, bit D7, of each register is the mute bit. When this bit is set, the output of the gain stage is silent. Muting the
amplifier does not stop the ADC capture stream.
There are 16 gain steps from 22.5 dB to 0 dB. The step size is 1.5 dB.
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