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參數(shù)資料
| 型號(hào)： | NT68P61A |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 8-Bit Microcontroller for Monitor (24K OTP ROM Type) |
| 中文描述： | 8位微控制器的監(jiān)視器（足金檢察官辦公室光盤形式） |
| 文件頁數(shù)： | 8/48頁 |
| 文件大?。?/td> | 1057K |
| 代理商： | NT68P61A |
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NT68P61A
8
3. OTP ROM: 24K X 8 bits
The OTP ROM storing application program code, executed by 6502 CPU, has a capacity of 24K X 8 bits, addressed from
$A000 to $FFFF. It is programmed by the universal EPROM writer through a conversion adapter.
In PROGRAMMING mode, OTP ROM is integrated with system and cannot be directly accessed. When using the OTP
ROM alone, first enter the PROGRAMMING mode by setting:
RESET
= VPP.
At this time, through multiplex pins, normal procedures are used to program and verify the OTP ROM block with the
universal programmer.
OTP ROM Mega Cell D.C. Electrical Characteristics (READ Mode)
(V
DD
= 5V , T
A
= 25
°
C, unless otherwise specified)
Symbol
Parameter
Min.
Typ.
Max.
Unit
Test Conditions
Note
V
IH
V
DD
-0.3
V
DD
+0.3
V
1
V
IL
Input Voltage
-0.3
0.3
V
1
I
IL
Input Current
+/-10
μ
A
I
OH
-400
μ
A
V
DD
=5V, V
OH
= 4.5V
I
OL
Output Voltage
1
μ
A
V
DD
=5V, V
OL
= 0.5V
I
DD
Operating Current
1
μ
A
f = 4MHz
2
ISTB1
Standby Current
100
μ
A
3
Notes: 1. All inputs and outputs are CMOS compatible
2. f = 4MHz, Iout = 0mA, CE = V
IH
, V
DD
= 5V
3. CE = V
IH
,
OE
= V
IL
, V
DD
= 5V
OTP ROM Mega Cell l A.C. Electrical Characteristics (READ Mode)
(V
DD
= 5V, T
A
= 25
°
C, unless otherwise specified)
Symbol
Parameter
Min.
Max.
Unit
Conditions
Tcyc
Cycle Time
250
ns
T12
Nonoverlap Time to PH1 & PH2
5
65
ns
Tacc
Address Access Time
145
ns
Tce
OTPCE to Output Valid
145
ns
4.5V < V
DD
< 5.5V
Tst
Output Data Setup Time
20
ns
Toh
Output Data Hold Time
0
ns
OTP ROM MEGA CELL A.C. Test Conditions
Output Load
1 CMOS Gate and CL = 10pF
Input Pulse Rise and Fall Times
10ns Max.
Input Pulse Levels
0V to 5V
Timing Measurement Reference Level
Inputs 0V and 5V outputs 0.3V and 4.7V
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