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參數(shù)資料
| 型號： | NT68P61A |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 8-Bit Microcontroller for Monitor (24K OTP ROM Type) |
| 中文描述： | 8位微控制器的監(jiān)視器（足金檢察官辦公室光盤形式） |
| 文件頁數(shù)： | 33/48頁 |
| 文件大?。?/td> | 1057K |
| 代理商： | NT68P61A |
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NT68P61A
33
13.3. Power Saving Mode Detect:
The VIDEO mode is listed below. Power saving is from mode 2 to mode 4. All modes can be detected by setting the
control register properly. Refer to Figure 15 control flow chart for software reference.
Mode
H-Sync
Active
Inactive
Active
Inactive
V-Sync
Active
Active
Inactive
Inactive
(1) Normal
(2) Stand by
(3) Suspend
(4) Off
Control bit description:
Addr.
$0005
Register
MD CON
INIT
07H
Bit7
-
-
Bit6
-
-
Bit5
-
-
Bit4
-
-
Bit3
-
INSEN
Bit2
-
HSEL
Bit1
Bit0
S/ C
S/ C
MD1/
2
MD1/
2
R
W
$0006
HV CON
2FH
HCNTOV
VCNTOV
HSYNCI
VSYNCI
HPOLI
VPOLI
HPOLO
HCL1
HCH1
VCL1
VCH1
VPOLO
HCL0
HCH0
VCL0
VCH0
R
W
R
R
R
R
W
$0007
$0008
$0009
$000A
$000B
HCNT L
HCNT H
VCNT L
VCNT H
SYNCON
00H
00H
00H
00H
FFH
HCL7
-
VCL7
-
HCL6
-
VCL6
-
HCL5
-
VCL5
-
-
HCL4
-
VCL4
-
HCL3
HCH3
VCL3
VCH3
HCL2
HCH2
VCL2
VCH2
HALFPOL
NOHALF
CLRHOV
ENHALF
CLRVOV
FRUN
CLRINTD
FRFREQ
CLRINTA
ENH
CLRINTE
ENV
CLRINTV
$0011
CLR FLG
00H
CLRINTS
CLRINTR
W
MDCON control register:
S/
C
: The SYNC MODE control. If the input of V & H
Sync are separate signals, set this bit to
'1' (system default). If the input is composite
signal, clear this bit. Under the COMPOSITE
mode,
NT68P61A will extract the V Sync form H Sync
signal.
HSEL
: When clearing this bit, system will reset
HCNTL|H counter to zero. The number of Hsync
pulse at the 8.192ms interval is obtained.
INSEN
:
User can clear this bit for inserting Hsync pulse
when processing the composite signal. System
will disable this function after reset.
HVCON control register:
HCNTOV:The overflow bit of H Sync. After setting
HSEL
bit
'1' without any input Vsync pulses and
there are more than 4096 Hsync pulses
coming ,this bit will be set. It will keep '1' and
user can clears it by setting CLRHOV bit to '1'
at the CLRFLG control register. After cleared,
the H Sync counter will reset to '0' and start
counting for every Hsync pulse.
VCNTOV: The overflow bit of V Sync. The operation is
the same as HCNTOV. After cleared, the
Vsync counter will reset to '0' and start
counting for every 8
μ
s.
HSYNCI & VSYNCI:User can instantaneously detect
input of H & V Sync pulse at any
time.
HPOLI & VPOLI:The polarity of input H & V Sync pulse
- '1' for positive polarity and '0' for
negative polarity.
HPOLO & VPOLO:To control the output polarity of H & V
Sync pulse - '1' for positive polarity
and '0' for negative polarity.
HCNTL|H & VCNTL|H control registers:
The 12 bits counter for H & V Sync pulse.
SYNCON control register:
ENH
&
ENV
: Enable the output of H & V Sync. The P06
& P07 will switch to VSYNCO & HSYNCO
output.
FRUN
: Open free run signal at the VSYNCO & HSYNCO
output.
FRFREQ
:Select the free run frequency of H Sync
output.
ENHALF
: P12 & P13 will switch to HALFHO & HALFHI
pin. The HALFHO will output the half signal at
the HALFHI pin with 50% duty.
NOHALF
:User must clear
ENHALF
first. The HALFHO
will output the same signal at the HALFHI
pin.
HALFPOL:User must clear
ENHALF
first and control
the
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