參數(shù)資料
型號(hào)： NT68P61A
廠商： Electronic Theatre Controls, Inc.
英文描述： 8-Bit Microcontroller for Monitor (24K OTP ROM Type)
中文描述： 8位微控制器的監(jiān)視器（足金檢察官辦公室光盤(pán)形式）
文件頁(yè)數(shù)： 29/48頁(yè)
文件大小： 1057K
代理商： NT68P61A
NT68P61A
29
13.2. Sync Processor Control Register:
Composite sync: User has to determine whether the
incoming signal is separate sync or composite sync and
set S/
C
&
HSEL
bit properly. If composite sync signal
is input, after set S/
C
to '0', the sync separator block will
be activated ( please refer figure 18). During Vsync pulse
the Hsync will be inserted Hsync pulse by hardware
circuit and the pulse width of inserted pulse is 2
μ
s fixed.
According to the last Hsync pulse outside the Vsync
pulse duration, the hardware will arrange the interval of
these hardware interpolated pulse. So the insertion of
these Hsync pulse will be continued inside the Vsync
pulse duration no matter what the Hsync pulse originally
exist or not. These inserted Hsync pulse have 0.5
μ
s
phase deviation maximum. The Vsync pulse can be
extracted by hardware from composite signal, and the
output of Vsync signal delay time will be limited bellow
20ns. For inserting Hsync pulse safely, the extracted
Vsync pulse will be widen about 9
μ
s. Because evenly
putting the Hsync pulse, the last inserted Hsync pulse
will have different frequency from original ones.
System will not implement this insertion function, user
must clear
INSEN
bit in the MD_CON control register to
activate this function.
After reset, the
HSEL
, S/
C
&
INSEN
bits default value
is HIGH and clear the VCNT | HCNT counter latches to
zero.
Polarity: The detection of Hsync or Vsync polarity is
achieved by hardware circuits sample the sync signal's
voltage level periodically. The user can read HPOLI &
VPOLI bit in HVCON register, from which bit = '1'
representing positive polarity and '0', negative polarity.
The user can read HSYNCI and VSYNCI bit in HVCON
register to detect H & V sync input signal. The user can
control the polarity of H & V sync output signal by
writing the appropriate data to the HPOLO and VPOLO
bits in the HVCON register, '1' represents positive
polarity and '0', negative polarity.
Sync output: In pin assignment, VSYNCO & HSYNCO
represent Vsync & Hsync output which are shared with
P06 & P07 respectively. If set
ENV
&
ENH
to '0' in
SYNCON register, P06 & P07 will act as VSYNCO &
HSYNCO pin. When input sync is separate signal, the
V/HSYNCO will output the same signal as input sync
signal without delay. But if input sync is composite
signal, the VSYNCO signal will have a delay time of
about 4
μ
s to 8
μ
s. The HSYNCO has no delay output and
still has Vsync pulse among Hsync pulse (i.e. the signal
on HSYNCI pin directly output to HSYNCO pin.)
Free run signal output: The user can set
FRUN
to '0' bit
in SYNCON register, then VSYNCO will output 61Hz
Vsync signal and HSYNCO will output 62.5KHz Hsync
signal default (Refer to Figure 20). When
FRFREQ
bit
clears to '0', the HSYNCO pin will output 41.7 KHz Hsync
signal. The free run signal has negative or positive
polarity depending on the HPOLO & VPOLO bit setting in
the HV_CON control register, '1' is positive and '0' is
negative polarity. After chip reset,
ENV
,
ENH
,
FRFREQ
&
FRUN
will enter HIGH state and P06 & P07 will act as
I/O pins.
Half frequency input and output: In this pin assignment,
when
ENHALF
sets to
'0' in SYNCON register, the
HALFHO pin will act as an output pin and output half of
input signal in the HALFHI pin with 50% duty
(Refer to Figure 21). If
NOHALF
sets
to '0', HALFHO will
output the same signal in the HALFHI pin and user can
control its polarity output of HALFHO by setting
HALFPOL bit, '1' for positive and '0' for negative polarity.
After chip reset,
ENHALF
,
NOHALF
& HALFPOL will be
in the HIGH state and P13 & P17 will act as I/O pins.
相關(guān)PDF資料
PDF描述
NT68P62 8-Bit Microcontroller for Monitor (32K OTP ROM Type)
NT68P62-01 8-Bit Microcontroller for Monitor (32K OTP ROM Type)
NT68P62U 8-Bit Microcontroller for Monitor (32K OTP ROM Type)
NT7181 LVDS Transmitter 24 Bit Color Host-LCD Display Panel Interface
NT7181F LVDS Transmitter 24 Bit Color Host-LCD Display Panel Interface
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
NT6C34CA 制造商:ASTEC 功能描述: 制造商:Emerson Network Power - Embedded Power 功能描述:
NT6DM32M16AD-T1 制造商:Nanya Technology Corporation 功能描述:MOBILE DRAM
NT6DM32M16BD-T1 制造商:NANYA TECHNOLOGY 功能描述:512M LPDDR SDRAM, 32Mx16, 200MHz 制造商:NANYA TECHNOLOGY 功能描述:NT6DM32 Series 1.8 V 512 Mb (32 Mb x 16) 200 MHz SDRAM - FBGA-60
NT6DM64M16BD-T1 制造商:Nanya Technology Corporation 功能描述:MEMORY IC
NT6DM8M32AC-T3 制造商:NANYA TECHNOLOGY 功能描述:NT6DM8M32 Series 1.8 V 256 Mb (8 M x 32) 166 Mhz SDRAM - BGA-90 制造商:NANYA TECHNOLOGY 功能描述:NT6DM8M32AC Series 256-Mbit (8 M x 32) 166 Mhz LPDDR SDRAM - BGA-90
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*