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參數(shù)資料
| 型號： | NT68P61A |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 8-Bit Microcontroller for Monitor (24K OTP ROM Type) |
| 中文描述： | 8位微控制器的監(jiān)視器（足金檢察官辦公室光盤形式） |
| 文件頁數(shù)： | 24/48頁 |
| 文件大?。?/td> | 1057K |
| 代理商： | NT68P61A |
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NT68P61A
24
12.2. Port1: P10 - P16
Port10-Port15 are 6-bit bi-directional CMOS I/O ports
with PMOS as the internal pull-up (Figure 6). Port16 is
an input pin only. Each bi-directional I/O pin may be bit
programmed as an input or output port without software
controlling the data direction register. When Port1 works
as output, the data to be output is latched to the port
data register and output to the pin. Port1 pins that have
'1's written to them are pulled high after reset.
P10, P11 are shared with AD0 & AD1 input pins
respectively. If user clears the
ENADX
bit in the ENDAC
control register to low, A/D converters will activate
simultaneously. After the chip is reset,
ENADX
bits enter
HIGH state and P10, P11 act as I/O pins.
P12, P13 are shared with half signals input and output
pins by accessing SYNCON control register. If user
clears the
ENHALF
bit to low, P13 will switch to HALFHI
pin (input pin) and P12 will switch to HALFHO pin
(output pin, Figure 8). Refer to half frequency function in
the H/V sync processor paragraph concerning HALFHI &
HALFHO pin. After the chip is reset, the
ENHALF
bits
will enter HIGH state and P12, P13 will act as I/O pins.
P16 has a Schmitt Trigger input buffer (Figure 9) and is
shared with the external interrupt pin if set the IEINTE bit
in IEX control register. Refer to 'Interrupt Controller'
section above for function details.
Addr.
Register
INIT
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
$0001
PT1
7FH
-
P16
P15
P14
P13
P12
P11
P10
RW
$000C
ENDAC
FFH
ENAD1
ENAD0
ENDK13
ENDK12
ENDK11
ENDK10
ENDK9
ENDK8
W
$000D
AD0 REG
C0H
CEND
CSTA
AD05
AD04
AD03
AD02
AD01
AD00
R
W
$000E
AD1 REG
00H
-
-
AD15
AD14
AD13
AD12
AD11
AD10
R
$000F
IEX
00H
-
-
IEINTS
IEINTD
IEINTA
IEINTR
IEINTE
IEINTV
W
Data Input
I/P
Vcc
Figure 9. Schmitt Input Structure
Vcc
I/O
Data Out
.
Data OE
Data In
Figure 10. I/O
Structure
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