參數(shù)資料
型號: NT68P61A
廠商: Electronic Theatre Controls, Inc.
英文描述: 8-Bit Microcontroller for Monitor (24K OTP ROM Type)
中文描述: 8位微控制器的監(jiān)視器(足金檢察官辦公室光盤形式)
文件頁數(shù): 36/48頁
文件大小: 1057K
代理商: NT68P61A
NT68P61A
36
Control bit description:
Addr.
Register
INIT
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
$0005
MD CON
07H
-
-
-
-
-
-
-
-
-
INSEN
-
HSEL
S/ C
S/ C
MD1/
2
MD1/
2
R
W
$000F
IEX
00H
-
-
IEINTS
IEINTD
IEINTA
IEINTR
IEINTE
IEINTV
W
$0010
IRQX
00H
-
-
IRQINTS
IRQINTD
IRQINTA
IRQINTR
IRQINTE
IRQINTV
R
$0011
CLR FLG
00H
CLRHOV
CLRVOV
CLRINTS
CLRINTD
CLRINTA
CLRINTR
CLRINTE
CLRINTV
W
$0014
II DAT
00H
SR7
SR6
SR5
SR4
SR3
SR2
SR1
SR0
RW
$0015
II STS
08H
-
-
START
START
STOP
STOP
ENDDC
TRX
RXAK
-
TXAK
R
W
MDCON control register:
MD1/
2
: Select the DDC mode - '1' for DDC1 and '0' for DDC2B mode. System will be DDC1 mode by default.
When transmission mode is changed form DDC1 to DDC2B, system automatically clears this bit.
IEX control register:
At DDC1 mode, only open INTD interrupt, as well as open INTS interrupt to detect if has changed to DDC2B mode.
II_DAT control register: Data buffer for transmission.
II_STS control register:
ENDDC
: When clearing this bit, system will activate DDC transmission. P30 & P31 will switch to SDA & SCL pin.
1
2
3
4
9
1
2
3
4
5
6
7
INTV
8
9
1
2
Vsync Pulse
ENDDC
(in IISTS register)
INTD
8
7
6
8
7
6
5
4
3
2
1
Shift
register
SDA
1
8
7
Null
Bit
5
4
3
1
8
6
2
Null
Bit
5
7
MSB
LSB
Second Byte Data
First Byte Data
Invalid data
User can load next byte data to IIDAT register
Load data in the IIDAT register to shift register
Figure 22. DDC1 Mode Timing Diagram
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