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參數(shù)資料
| 型號： | NT68P61A |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 8-Bit Microcontroller for Monitor (24K OTP ROM Type) |
| 中文描述： | 8位微控制器的監(jiān)視器（足金檢察官辦公室光盤形式） |
| 文件頁數(shù)： | 16/48頁 |
| 文件大小： | 1057K |
| 代理商： | NT68P61A |
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NT68P61A
16
6. Timing Generator
This block generates the system timing and control signal to be supplied to the CPU and on-chip peripherals. A crystal
quartz, ceramic resonator, or an external clock signal provided to the OSCI pin generates 8MHz system clock,
(4 MHz for CPU), Although internal circuits have a feedback resistor and capacitor included, components may be
externally added to ensure proper operation. The typical clock frequency is 8MHz. This frequency will affect the operation
of on-chip peripherals whose operating frequency is based on the system clock .
8MHz
OSCI
OSCO
NT68P61A
OSCI
NT68P61A
(1)
(2)
Unconnected
External Clock
OSCO
Figure 2. Oscillator Connections
7. A/D Converter
The analog to digital converter is a single 6-bit successive approximation converter. Analog voltage is supplied from
external sources to the A/D input pins and the results of the conversion are stored in the 6-bit data latch registers
($000D & $000E). The A/D converter is controlled by the control bits in the A/D control register ENDAC. Refer to the A/D
channel format table A/D input pins activation. A conversion is started by setting a '0' to the CONVERSION START bit
(
CSTA
) in the A/D control register ($000D). This automatically sets the CONVERSION END bit (
CEND
) to '1'. When a
conversion has been finished,
CEND
bit automatically clears to '0'. The A/D conversion data in the AD LATCH registers
($000D & $000E) is valid digital data.
The analog voltage to be measured should be stable during the conversion operation. The variation should exceed
1/2 LSB for accuracy in measurement. Please refer Figure 3 for checking the linearity of A/D.
A/D Channel Format Table
ENAD1
ENAD0
P11 line
P10 line
0
0
AD1
AD0
0
1
AD1
P10
1
0
P11
AD0
1
1
P11
P10
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