參數(shù)資料
型號(hào): MX28F160C3BXAC-90
廠商: MACRONIX INTERNATIONAL CO LTD
元件分類: DRAM
英文描述: 16M-BIT [1M x16] CMOS SINGLE VOLTAGE 3V ONLY FLASH MEMORY
中文描述: 1M X 16 FLASH 3V PROM, 90 ns, PBGA48
封裝: 8 X 6 MM, 1.20 MM HEIGHT, 0.75 MM PITCH, MO-207, CSP-48
文件頁(yè)數(shù): 5/44頁(yè)
文件大?。?/td> 429K
代理商: MX28F160C3BXAC-90
5
P/N:PM0867
MX28F160C3T/B
REV. 1.2, MAR. 17, 2004
Table 1. Pin Description
Symbol
A0-A19
Type
input
Description and Function
Address inputs for memory address. Data pin float to high-impedance when the chip is
deselected or outputs are disable. Addresses are internally latched during a write or
erase cycle.
Data inputs/outputs: Inputs array data on the second CE and WE cycle during a pro-
gram command. Data is internally latched. Outputs array and configuration data. The
data pin float to tri-state when the chip is de-selected.
Chip Enable : Activates the device's control logic, input buffers, and sense amplifiers.
CE high de-selects the memory device and reduce power consumption to standby
level. CE is active low.
Reset/Deep Power Down: when RP=VIL, the device is in reset/deep power down mode,
which drives the outputs to High Z, resets the WSM and minimizes current level.
When RP=VIH, the device is normal operation. When RP transitions from VIL to VIH,
the device defaults to the read array mode.
Write Enable: to control write to CUI and array sector. WE=VIL becomes active. The
data and addresses are latched on the rising edge of the second WE pulse.
Program/Erase Power Supply:(1.65V~3.6V or 11.4V~12.6V)
Lower VPP<VPPLK, to protect any contents against Program and Erase Command.
Set VPP=VCC for in-system Read, Program and Erase Operation.
Raise VPP to 12V
±
5% for faster program and erase in a production environment.
Output enable: gates the device's outputs during a real cycle.
Write Protect: When WP is VIL, the sectors marked Lock Down can't be unlocked
through software. When WP is VIH, the lock down mechanism is disable and sectors
previously locked down are now locked and can be unlocked and locked through soft-
ware. After WP goes low, any sectors previously marked lock down revert to that state.
Device power supply: (2.7V~3.6V).
I/O Power Supply: supplies for input/output buffers. (VCCQ must be tied to VCC)
Ground voltage: all the GND pin shall not be connected.
DQ0-DQ15
input/output
CE
input
RP
input
WE
input
VPP
input/supply
OE
WP
input
input
VCC
VCCQ
GND
supply
input
supply
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