參數(shù)資料
型號(hào)： MX28F160C3BXAC-90
廠商： MACRONIX INTERNATIONAL CO LTD
元件分類： DRAM
英文描述： 16M-BIT [1M x16] CMOS SINGLE VOLTAGE 3V ONLY FLASH MEMORY
中文描述： 1M X 16 FLASH 3V PROM, 90 ns, PBGA48
封裝： 8 X 6 MM, 1.20 MM HEIGHT, 0.75 MM PITCH, MO-207, CSP-48
文件頁(yè)數(shù)： 17/44頁(yè)
文件大小： 429K
代理商： MX28F160C3BXAC-90
17
P/N:PM0867
MX28F160C3T/B
REV. 1.2, MAR. 17, 2004
Table 6. Status Register Definition
SR.7 = WRITE STATE MACHINE STATUS (WSMS)
1 = Ready
0 = Busy
SR.6 = SECTOR ERASE SUSPEND STATUS (SESS)
1 = Sector ERASE Suspended
0 = Sector Erase in Progress/Completed
SR.5 = ERASE STATUS (ES)
1 = Error in Programming
0 = Successful Sector Erase or Clear Sector Lock-
Bits
SR.4 = PROGRAM STATUS (PS)
1 = Error in Programming
0 = Successful Programming
SR.3 = VPP STATUS (VPPS)
1 = VPP Low Detect, Operation Abort
0 = VPP OK
SR.2 = PROGRAM SUSPEND STATUS (PSS)
1 = Program Suspended
0 = Program in Progress/Completed
SR.1 = SECTOR LOCK STATUS (SLS)
1 =Program/Erase attempted an a locked sector;
operation aborted
0 = No operation to locked sectors
SR.0 = RESERVED FOR FUTURE ENHANCEMENTS
(R)
NOTES:
Check WSM bit first to determine word program or sec-
tor Erase completion, before checking Program or Erase
Status bits.
When Sector Erase Suspend is issued, WSM halts ex-
ecution and sets both WSMS and SESS bits to "1". SESS
bit remains set to "1" until an Sector Erase Resume
command is issued.
When this bit (SR.5) is set to "1", it means WSM is
unable to verify successful sector erasure.
When this bit is set to "1", WSM has attempted but failed
to program a word.
The WSM interrogates VPP level only after the Program
or Erase command sequences have been entered and
informs the system if VPP has not been switched on.
SR.3 bit is not guaranteed to report accurate feedback
between VPPLK and VPP1 min.
When program suspend is issued, WSM halts the ex-
ecution and sets both WSMS and PSS bits to "1". SR.2
remains set to "1" until a Program Resume command is
issued.
If a program or erase operation is attempted to one of
the locked sectors, this bit is set by the WSM. The op-
eration specified is aborted and the device is returned to
read status mode.
SR. 0 is reserved for future use and should be masked
out when polling the status register.
WSMS
SESS
ES
PS
VPPS
PSS
SLS
R
7
6
5
4
3
2
1
0
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