MT90869
Data Sheet
6
Zarlink Semiconductor Inc.
BSTo16 - 31
E3, E4, F1, F2, F3,
G1, G2, G3, G4, H1,
H2, H3, J1, J2, J3,
J4
Backplane Serial Output Streams 16 to 31 (5V Tolerant Three-state Outputs).
In Non-32Mb/s Mode, these pins output serial TDM data streams at a data-rate of:-
16.384 Mb/s (with 256 channels per stream),
8.192 Mb/s (with 128 channels per stream),
4.096 Mb/s (with 64 channels per stream), or
2.048Mb/s (with 32 channels per stream).
The data-rate is independently programmable for each output stream.
These pins are unused when the 32Mb/s Mode is selected.
Refer to descriptions of the
BORS
and
ODE
pins for control of the output High or
High-Impedance state.
BCSTo0-3
C14, A15, B15, C15
Backplane Output Channel High Impedance Control (5V Tolerant Three-state
Outputs).
Active high output enable which may be used to control external
buffering individually for a set of backplane output streams on a per channel basis.
In non-32Mb/s mode (stream rates 2Mb/s to 16Mb/s):
BCSTo0 is the output enable for BSTo[0,4,8,12,16,20,24,28],
BCSTo1 is the output enable for BSTo[1,5,9,13,17,21,25,29],
BCSTo2 is the output enable for BSTo[2,6,10,14,18,22,26,30],
BCSTo3 is the output enable for BSTo[3,7,11,15,19,23,27,31].
In 32Mb/s mode (stream rate 32Mb/s):
BCSTo0 is the output enable for BSTo[0,4,8,12],
BCSTo1 is the output enable for BSTo[1,5,9,13],
BCSTo2 is the output enable for BSTo[2,6,10,14],
BCSTo3 is the output enable for BSTo[3,7,11,15].
Refer to descriptions of the
BORS
and
ODE
pins for control of the output High or
High-Impedance state.
FP8i
U14
Frame Pulse Input (5V Tolerant).
This pin accepts the Frame Pulse signal. The
pulse width may be active for 122ns or 244ns at the frame boundary and the
Frame Pulse Width bit (FPW) of the Control Register must be set Low (default) for
a 122ns and set High for a the 244ns pulse condition.The device will automatically
detect whether an
ST-BUS
or
GCI-BUS
style frame pulse is applied.
C8i
W12
Master Clock Input (5V Tolerant).
This pin accepts a 8.192MHz clock. The
internal Frame Boundary is aligned with the clock falling or rising edge, as
controlled by the C8IPOL bit of the control register.
CS
B11
Chip Select (5V Tolerant).
Active low input used by the microprocessor to enable
the microprocessor port access. This input is internally set low during a device
RESET.
DS
A11
Data Strobe (5V Tolerant).
This active low input works in conjunction with CS to
enable the microprocessor port read and write operations.
R/W
C11
Read/Write (5V Tolerant).
This input controls the direction of the data bus lines
(D0-D15) during a microprocessor access.
A0 - A14
D5, C6, A6, D7, C7,
B7, C8, B8, A8, D9,
B9, A9, D10, C10,
A10
Address 0 - 14 (5V Tolerant).
These pins form the 15-bit address bus to the
internal memories and registers.
A0 = LSB
D0 - D15
V10, Y9, W9, V9,U9,
Y8, W8, V8, W7, V7,
U7, Y6, W6, V6, Y5,
W5
Data Bus 0 - 15 (5V Tolerant).
These pins form the 16-bit data bus of the
microprocessor port.
D0 = LSB
DTA
A13
Data Transfer Acknowledgment (5V Tolerant).
This active low output indicates
that a data bus transfer is complete. A pull-up resistor is required to hold a HIGH
level. (Max. I
OL
= 10mA).
Pin Description (continued)
Name
Package
Coordinates
Description