參數(shù)資料
型號: MT90869
廠商: Zarlink Semiconductor Inc.
英文描述: Flexible 16K Digital Switch (F16kDX)
中文描述: 靈活的16K的數(shù)字交換機(jī)(F16kDX)
文件頁數(shù): 49/76頁
文件大?。?/td> 1316K
代理商: MT90869
Data Sheet
MT90869
49
Zarlink Semiconductor Inc.
13.5.1
Local Input Delay Bits 4-0 (LID4 - LID0)
These five bits define the delay from the bit boundary that the receiver uses to sample each input. Input bit delay
adjustment can range up to 7
3
/
4
bit periods forward, with resolution of
1
/
4
bit period.
This can be described as:
LIDn(4:0) = (no. of bits delay) / 4
For example, if LIDn(4:0) is set to 10011 (19), the input bit delay = 19 *
1
/
4
= 4
3
/
4.
Table 22, “Local Input Bit Delay Programming Table,” on page 49, illustrates the bit delay selection.
Corresponding Delay Bits
Data Rate
0 (Default)
1/4
1/2
3/4
1
1 1/4
1 1/2
1 3/4
2
2 1/4
2 1/2
2 3/4
3
3 1/4
3 1/2
3 3/4
4
4 1/4
4 1/2
4 3/4
5
5 1/4
5 1/2
5 3/4
6
6 1/4
6 1/2
6 3/4
7
7 1/4
7 1/2
7 3/4
LID4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
LID3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
LID2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
LID1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
LID0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Table 22 - Local Input Bit Delay Programming Table
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