MT90869
Data Sheet
20
Zarlink Semiconductor Inc.
4.0
Port High Impedance Control
4.1
Local Port High Impedance Control
The input pin,
LORS
, selects whether the Local output streams,
LSTo0-31
are set to high impedance at the output
of the MT90869 itself, or are always driven (active HIGH or active LOW) and a high impedance state, if required on
a per-channel basis, is invoked through an external interface circuit controlled by the
LCSTo0-3
signals. Setting
LORS
to a LOW state will configure the output streams,
LSTo0-31,
to transmit bi-state channel data with per-
channel high-impedance determined by external circuits under the control of the
LCSTo0-3
outputs. Setting
LORS
to a HIGH state will configure the output streams,
LSTo0-31,
of the MT90869 to invoke a high-impedance output on
a per-channel basis.
The state of the
LORS
pin is detected and the MT90869 configured accordingly during a
RESET
operation, e.g.
following power-up. The LORS pin is asynchronous input and is expected
to be hard-wired for a particular system
application, although it may be driven under logic control if preferred.
4.1.1
LORS Set LOW
The data (channel control bit) transmitted by
LCSTo0-3
replicates the Local Output Enable Bit (
LE
) of the Local
Connection Memory, with a LOW state indicating the channel to be set to High Impedance. Section 12.3, Local
Connection Memory Bit Definition, refers.
The
LCSTo0-3
outputs transmit serial data (channel control bits) at 16.384Mb/s, with each bit representing the per-
channel high impedance state for specific streams. Eight output streams are allocated to each control line as follows:
(See also
Pin Description
)
LCSTo0 outputs the channel control bits for streams LSTo0, 4, 8, 12, 16, 20, 24 and 28.
LCSTo1 outputs the channel control bits for streams LSTo1, 5, 9, 13, 17, 21, 25 and 29.
LCSTo2 outputs the channel control bits for streams LSTo2, 6, 10, 14, 18, 22, 26 and 30.
LCSTo3 outputs the channel control bits for streams LSTo3, 7, 11, 15, 19, 23, 27 and 31.
The Channel Control Bit location, within a frame period, for each channel of the Local output streams is presented
in Table 2, LCSTo Allocation of Channel Control Bits to the Output Streams
.
As an aid to the description, the channel control bit for a single channel on specific streams is presented, with
reference to Table 2:
(1) The Channel Control Bit corresponding to Stream 0, Channel 0,
LSTo0_Ch0,
is transmitted on
LCSTo0
and is
advanced, relative to the Frame Boundary, by 10 periods of
C16o
.
(2) The Channel Control Bit corresponding to Stream 28, Channel 0,
LSTo28_Ch0,
is transmitted on
LCSTo0
in
advance of the Frame Boundary by three periods of output clock,
C16o
. Similarly, the Channel Control Bits for
LSTo29_Ch0
,
LSTo30_Ch0
and
LSTo31_Ch0
are advanced relative to the Frame Boundary by three periods of
C16o
, on
LCSTo1
,
LCSTo2
and
LCSTo3
, respectively.
The
LCSTo0-3
outputs data at a constant data-rate of 16.384Mb/s, independent of the data-rate selected for the
individual output streams,
LSTo0-31
. Streams at data-rates lower than 16.384Mb/s will have the value of the
respective channel control bit repeated for the duration of the channel. The bit will be repeated twice for 8.192Mb/s
streams, four times for 4.096Mb/s streams and eight times for 2.048Mb/s streams. The channel control bit is not
repeated for 16.384Mb/s streams.