參數(shù)資料
型號: MT90869
廠商: Zarlink Semiconductor Inc.
英文描述: Flexible 16K Digital Switch (F16kDX)
中文描述: 靈活的16K的數(shù)字交換機(jī)(F16kDX)
文件頁數(shù): 41/76頁
文件大?。?/td> 1316K
代理商: MT90869
Data Sheet
MT90869
41
Zarlink Semiconductor Inc.
13.0
Detailed Register Description
This section describes the registers that are used in the device.
13.1
Control Register (CR)
Address 0000h.
The control register defines which memory is to be accessed. It initiates the memory block programming mode and
selects the backplane data rate mode. The Control Register (
CR
) is configured as follows:
00C3
H
Local BER Start Send Register, LBSSR
00C4
H
Local Transmit BER Length Register, LTXBLR
00C5
H
Local Receive BER Length Register, LRXBLR
00C6
H
Local BER Start Receive Register, LBSRR
00C7
H
Local BER Count Register, LBCR
00C8
H
Backplane BER Start Send Register, BBSSR
00C9
H
Backplane Transmit BER Length Register, BTXBLR
00CA
H
Backplane Receive BER Length Register, BRXBLR
00CB
H
Backplane BER Start Receive Register, BBSRR
00CC
H
Backplane BER Count Register, BBCR
00CD
H -
00EC
H
Local Input Bit rate Register 0, LIBRR0 - Register 31, LIBRR31
00ED
H -
010C
H
Local Output Bit rate Register 0, LOBRR0 - Register 31, LOBRR31
010D
H -
012C
H
Backplane Input Bit rate Register 0, BIBRR0 - Register 31, BIBRR31
012D
H -
014C
H
Backplane Output Bit rate Register 0, BOBRR0 - Register 31, BOBRR31
014D
H
Memory BIST Register, MBISTR
3FFF
H
Revision control register, RCR
Bit
Name
Reset
Description
15-9
8
Reserved
FPW
0
0
Reserved
.
Frame Pulse Width
When LOW, an input frame pulse width of 122ns shall be applied to FP8i. When
HIGH, an input frame pulse width of 244ns shall be applied to FP8i.
32MHz Mode
When LOW, Backplane streams (BSTi0-31 and BSTo0-31) may be individually
programmed for data-rates of 2, 4, 8, or 16Mb/s. When HIGH, the Backplane
streams (BSTi0-15 and BSTo0-15) operate in 32Mb/s mode.
7
MODE32
0
Table 16 - Control Register Bits
A14 - A0
Register
Table 15 - Address Map for Register (A14 = 0) (continued)
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