參數(shù)資料
型號(hào)： MT90869
廠商： Zarlink Semiconductor Inc.
英文描述： Flexible 16K Digital Switch (F16kDX)
中文描述： 靈活的16K的數(shù)字交換機(jī)（F16kDX）
文件頁(yè)數(shù)： 46/76頁(yè)
文件大?。?/td> 1316K
代理商： MT90869
MT90869
Data Sheet
46
Zarlink Semiconductor Inc.
13.3
Bit Error Rate Test Control Register (BERCR)
Address 0002h.
The BER control register controls backplane and local port BER testing. It independently enables and disables
transmission and reception. It is configured as follows:
Bit
Name
RESET
Description
15-12
Reserved
0
Reserved.
11
LOCKB
0
Backplane Lock (READ ONLY).
This bit is automatically set HIGH when the receiver has locked to the
incoming data sequence. The bit is reset by a LOW to HIGH transition on
SBERRXB.
10
PRSTB
0
PBER Reset for Backplane.
A LOW to HIGH transition initializes the backplane BER generator to the seed
value.
9
CBERB
0
Clear Bit Error Rate Register for Backplane.
A LOW to HIGH transition in this bit resets the backplane internal bit error
counter and the backplane bit error (BBERR) register to zero.
8
SBERRXB
0
Start Bit Error Rate Receiver for Backplane.
A LOW to HIGH transition enables the Backplane BER receiver. The receiver
monitors incoming data for reception of the seed value. When detected, the
LOCK state is indicated (LOCKB) and the receiver compares the incoming
bits with the reference generator for bit equality and increments the
Backplane Bit error Register (BBCR) on each failure. When set LOW, bit
comparison is disabled and the error count is frozen. The error count is stored
in the Backplane Bit Error Register (BBCR).
7
SBERTXB
0
Start Bit Error Rate Transmitter for Backplane.
A LOW to HIGH transition starts the BER transmission. When set LOW,
transmission is disabled.
6
PRBSB
0
BER Mode Select for Backplane.
When set HIGH, a PRBS sequence of length 2
23
-1 is selected for the
Backplane port. When set LOW, a PRBS sequence of length 2
15
-1 is selected
for the Backplane port.
5
LOCKL
0
Local Lock (READ ONLY).
This bit is automatically set HIGH when the receiver has locked to the
incoming data sequence. The bit is reset by a LOW to HIGH transition on
SBERRXL
4
PRSTL
0
PBER Reset for Local.
A LOW to HIGH transition initializes the local BER generator to the seed
value.
3
CBERL
0
Clear Bit Error Rate Register for Local.
A LOW to HIGH transition resets the local internal bit error counter and the
local bit error (LBERR) register to zero.
Table 18 - Bit Error Rate Test Control Register (BERCR) Bits
相關(guān)PDF資料
PDF描述
MT90869AG Flexible 16K Digital Switch (F16kDX)
MT90870 Flexible 12 k Digital Switch (F12kDX)
MT90871AV Flexible 8K Digital Switch (F8KDX)
MT90871 Flexible 8K Digital Switch (F8KDX)
MT90883 TDM to Packet Processors
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MT90869AG 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 16KX16K/8KX8K 1.8V/3.3V 272BGA - Trays 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC DGTL SWITCH F16KDX 272PBGA 制造商:Microsemi Corporation 功能描述:IC DGTL SWITCH F16KDX 272PBGA
MT90869AG2 制造商:Microsemi Corporation 功能描述:PB FREE 8K X 8K DIGITAL SWITCH 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 16KX16K/8KX8K 1.8V/3.3V 272BGA - Trays 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC DGTL SWITCH F16KDX 272PBGA 制造商:Microsemi Corporation 功能描述:IC DGTL SWITCH F16KDX 272PBGA
MT90870 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Flexible 12 k Digital Switch (F12kDX)
MT90870AG 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 12K X 12K/8K X 4K 1.8V/3.3V 272BGA - Trays
MT90870AG2 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 12K X 12K/8K X 4K 1.8V/3.3V 272BGA - Trays
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