參數(shù)資料
型號: MT90869
廠商: Zarlink Semiconductor Inc.
英文描述: Flexible 16K Digital Switch (F16kDX)
中文描述: 靈活的16K的數(shù)字交換機(F16kDX)
文件頁數(shù): 51/76頁
文件大小: 1316K
代理商: MT90869
Data Sheet
MT90869
51
Zarlink Semiconductor Inc.
13.7
Backplane Input Bit Delay Registers (BIDR0 to BIDR31)
Address 0063h to 0082h
Thirty-two backplane input delay registers (BIDR0 to BIDR31) allow users to program the input bit delay for the
backplane input data streams BSTi0-31. The possible adjustment is 7 3/4 of the data rate, in steps of 1/4 of the
data rate. The data rate can be either 2Mb/s, 4Mb/s, 8Mb/s, 16Mb/s, or 32Mb/s.
The
BIDR0 to BIDR31
registers are configured as follows:
Table 25 - Backplane Input Bit Delay Register (BIDRn) Bits
13.7.1
Backplane Input Delay Bits 4-0 (BID4 - BID0)
These five bits define how long in the cycle the serial interface receiver takes to recognize and stores the bit 0 from
the BSTi input pins: i.e., start assuming a new frame. Input bit delay adjustment can range up to 7
3
/
4
bit periods
forward with resolution of
1
/
4
bit period.
This can be described as
BIDn(4:0) = (no. of bits delay) / 4
For example, if BID(4:0) is set to 10011 (19), the input
bit delay = 19 *
1
/
4
= 4
3
/
4.
Table 26 illustrates the bit delay selection.
BIDRn Bit
(where n = 0 to 31 for Non-32Mb/s
Mode, n = 0 to15 for 32Mb/s Mode)
Name
Reset
Description
15-5
Reserved
0
Reserved
4-0
BID(4:0)
0
Backplane Input Bit Delay Register
The binary value of these bits refers to the input bit
delay value for the backplane input stream
Corresponding Delay Bits
Data Rate
0 (Default)
1/4
1/2
3/4
1
1 1/4
1 1/2
1 3/4
2
2 1/4
2 1/2
2 3/4
3
3 1/4
3 1/2
3 3/4
BID4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BID3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
BID2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
BID1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
BID0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Table 26 - Backplane Input Bit Delay Programming Table
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