參數(shù)資料
型號： MT90826AV
廠商： ZARLINK SEMICONDUCTOR INC
元件分類： 路由/交換
英文描述： Quad Digital Switch
中文描述： TELECOM, DIGITAL TIME SWITCH, PBGA144
封裝： 13 X 13 MM, 1.25 MM HEIGHT, MO-192, LBGA-144
文件頁數(shù)： 37/46頁
文件大?。?/td> 571K
代理商： MT90826AV
MT90826
Data Sheet
37
Zarlink Semiconductor Inc.
Note: 1. High Impedance is measured by pulling to the appropriate rail with R
L
, with timing corrected to cancel time taken to discharge C
L
Figure 8 - ST-BUS Timing for Stream rate of 16.384 Mbps
AC Electrical Characteristics
- Serial Streams for ST-BUS
Characteristic
Sym.
Min.
Typ.
Max.
Units
Test Conditions
1
Input Data Sample Point (Data rate of
16 Mbps)
Input Data Sample Point (Data rate of
8 Mbps)
Input Data Sample Point (Data rate of
4 Mbps)
Input Data Sample Point (Data rate of
2 Mbps)
STi Set-up Time (Data rate of 16 Mbps)
STi Hold Time (Date rate of 16 Mbps)
STi Set-up Time (Date rate of 2, 4 or 8 Mbps)
STi Hold Time (Date rate of 2, 4 or 8 Mbps)
t
IDS_16
30
ns
2
t
IDS_8
91
ns
3
t
IDS_4
183
ns
4
t
IDS_2
366
ns
5
6
7
8
t
SIS_16
t
SIH_16
t
SIS
t
SIH
0
8
0
8
ns
ns
ns
ns
9
STo Delay - Active to Active
t
SOD
8
11
30
43
ns
C
L
=30pF
C
L
=200pF
R
L
=1K, C
L
=200pF,
See Note 1
R
L
=1K, C
L
=200pF,
See Note 1
10 Output Driver Enable (ODE) Delay
t
ODE
35
ns
11 STo delay - Active to High-Z
- High-Z to Active
t
DZ,
t
ZD
35
ns
V
TT
V
TT
F0i
CLK
(16.384 MHz)
t
FPW
STo
(16 Mbps)
STi
(16 Mbps)
t
FPH
t
SOD
t
SIH_16
t
CH
t
CL
t
FPS
t
CP
t
SIS_16
V
V
LM
V
TT
V
TT
t
r
t
f
Ch0
Bit5
Ch0
Bit6
Ch0
Bit7
Ch255
Bit0
Ch255
Bit1
Ch0
Bit2
Ch0
Bit3
Ch0
Bit4
Ch0
Bit1
Ch0
Bit5
Ch0
Bit6
Ch0
Bit7
Ch255
Bit0
Ch255
Bit1
Ch0
Bit2
Ch0
Bit3
Ch0
Bit4
Ch0
Bit1
t
IDS_16
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參數(shù)描述
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