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參數(shù)資料
| 型號： | MT90826AV |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 路由/交換 |
| 英文描述： | Quad Digital Switch |
| 中文描述： | TELECOM, DIGITAL TIME SWITCH, PBGA144 |
| 封裝： | 13 X 13 MM, 1.25 MM HEIGHT, MO-192, LBGA-144 |
| 文件頁數(shù)： | 17/46頁 |
| 文件大?。?/td> | 571K |
| 代理商： | MT90826AV |
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MT90826
Data Sheet
17
Zarlink Semiconductor Inc.
3.4 Memory Block Programming
The MT90826 provides users with the capability of initializing the entire connection memory block in two frames.
Bits 13 to 15 of every connection memory location will be programmed with the pattern stored in bits 13 to 15 of the
control register.
The block programming mode is enabled by setting the memory block program (MBP) bit of the control register
high. When the block programming enable (BPE) bit of the control register is set to high, the block programming
data will be loaded into the bits 13 to 15 of every connection memory location. The other connection memory bits
(bit 0 to 12) are loaded with zeros. When the memory block programming is complete, the device resets the BPE bit
to zero.
3.5 Bit Error Rate Monitoring
The MT90826 allows users to perform bit error rate monitoring by sending a pseudo random pattern to a selected
ST-BUS output channel and receiving the pattern from a selected ST-BUS input channel. The pseudo random
pattern is internally generated by the device with the polynomial of 2
15
-1.
Users can select the pseudo random pattern to be presented on a ST-BUS channel by programming the TM0 and
TM1 bits in the connection memory. When TM0 and TM1 bits are high, the pseudo random pattern is output to the
selected ST-BUS output channel. The pseudo random pattern is then received by a ST-BUS input channel which is
selected using the BSA and BCA bits in the bit error rate input selection register (BISR). An internal bit error counter
keeps track of the error counts which is then stored in the bit error count register (BECR).
The bit error test is enabled and disabled by the SBER bit in the control register. Setting the bit from zero to one
initiates the bit error test and enables the internal bit error counter. When the bit is programmed from one to zero,
A13
Stream Address (ST0-31)
Channel Address (Ch0-255)
A12
A11
A10
A9
A8
Stream
Location
A7
A6
A5
A4
A3
A2
A1
A0
Channel
Location
1
1
1
1
1
1
1
1
1
.
.
.
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
.
.
.
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
.
.
.
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
.
.
.
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
.
.
.
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
.
.
.
0
1
0
1
0
1
0
1
0
1
Stream 0
Stream 1
Stream 2
Stream 3
Stream 4
Stream 5
Stream 6
Stream 7
Stream 8
.
.
.
Stream 22
Stream 23
Stream 24
Stream 25
Stream 26
Stream 27
Stream 28
Stream 29
Stream 30
Stream 31
0
0
.
.
0
0
0
0
.
.
0
0
0
0
.
0
0
1
1
.
1
1
0
0
.
.
0
0
0
0
.
.
0
0
1
1
.
1
1
0
0
.
1
1
0
0
.
.
0
0
1
1
.
.
1
1
0
0
.
1
1
0
0
.
1
1
0
0
.
.
1
1
0
0
.
.
1
1
0
0
.
1
1
0
0
.
1
1
0
0
.
.
1
1
0
0
.
.
1
1
0
0
.
1
1
0
0
.
1
1
0
0
.
.
1
1
0
0
.
.
1
1
0
0
.
1
1
0
0
.
1
1
0
0
.
.
1
1
0
0
.
.
1
1
0
0
.
1
1
0
0
.
1
1
0
1
.
.
0
1
0
1
.
.
0
1
0
1
.
0
1
0
1
.
0
1
Ch 0
Ch 1
.
.
Ch 30
Ch 31 (Note 2)
Ch 32
Ch 33
.
.
Ch 62
Ch 63 (Note 3)
Ch 64
Ch 65
.
Ch 126
Ch 127 (Note 4)
Ch 128
Ch 129
.
Ch 254
Ch 255 (Note 5)
1. Bit A13 must be high for access to data and connection memory positions. Bit A13 must be low for access to registers.
2. Channels 0 to 31 are used when serial stream is at 2Mbps.
3. Channels 0 to 63 are used when serial stream is at 4Mbps
4. Channels 0 to 127 are used when serial stream is at 8Mbps
5. Channels 0 to 255 are used when serial stream is at 16Mbps
Table 4 - Address Map for Memory Locations (A13 = 1)
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