參數(shù)資料
型號: MT90826AV
廠商: ZARLINK SEMICONDUCTOR INC
元件分類: 路由/交換
英文描述: Quad Digital Switch
中文描述: TELECOM, DIGITAL TIME SWITCH, PBGA144
封裝: 13 X 13 MM, 1.25 MM HEIGHT, MO-192, LBGA-144
文件頁數(shù): 1/46頁
文件大小: 571K
代理商: MT90826AV
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2003-2005, Zarlink Semiconductor Inc. All Rights Reserved.
Features
4,096
×
4,096 channel non-blocking switching at
8.192 or 16.384 Mbps
Per-channel variable or constant throughput
delay
Accepts 32 ST-BUS streams of 2.048 Mbps,
4.096 Mbps, 8.192 Mbps or 16.384 Mbps
Split Rate mode provides a rate conversion option
to convert data from one rate to another rate
Automatic frame offset delay measurement for
ST-BUS input streams
Per-stream input delay programming
Per-stream output advancement programming
Per-channel high impedance output control
Bit Error Monitoring on selected ST-BUS input
and output channels.
Per-channel message mode
Connection memory block programming
IEEE-1149.1 (JTAG) Test Port
3.3 V local I/O with 5 V tolerant inputs and TTL
compatible outputs
Applications
Medium switching platforms
CTI application
Voice/data multiplexer
Digital cross connects
WAN access system
Wireless base stations
August 2005
Ordering Information
MT90826AL
MT90826AG
MT90826AV
MT90826AL1
160 Pin MQFP
160 Ball PBGA
144 Ball LBGA
160 Pin MQFP*
*Pb Free Matte Tin
-40
°
C to +85
°
C
Trays
Trays
Trays
Trays
MT90826
Quad Digital Switch
Data Sheet
Figure 1 - Functional Block Diagram
Test Port
STo0
STo1
STo31
STi0/FEi0
STi1/FEi1
STi31/FEi31
Parallel
to
Serial
Converter
Output
MUX
Microprocessor Interface
Timing Unit
Internal
Registers
F0i
DS
CS
R/W
A13-A0
DTA
D15-D0
ODE
V
SS
Connection
Memory
CLK
V
DD
TDI
TDO
RESET
TCK
TRST
Serial
to
Parallel
Converter
TMS
Multiple Buffer
Data Memory
PLLV
SS
PLLV
DD
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