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參數(shù)資料
| 型號： | MT90826AV |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 路由/交換 |
| 英文描述： | Quad Digital Switch |
| 中文描述： | TELECOM, DIGITAL TIME SWITCH, PBGA144 |
| 封裝： | 13 X 13 MM, 1.25 MM HEIGHT, MO-192, LBGA-144 |
| 文件頁數(shù)： | 20/46頁 |
| 文件大?。?/td> | 571K |
| 代理商： | MT90826AV |
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MT90826
Data Sheet
20
Zarlink Semiconductor Inc.
4
MS
Memory Select.
When 0, connection memory is selected for read or write operations.
When 1, the data memory is selected for read operations and connection memory is
selected for write operations. (No microprocessor write operation is allowed for the
data memory.)
For data memory read operations, two consecutive microprocessor cycles are
required. The read address should remain the same for the two consecutive read
cycles. The data memory content from the first read cycle should be ignored. The
correct data memory content will be presented to the data bus on the second read
cycle.
3
OSB
Output Stand By.
This bit controls the device output drivers.
OSB bit ODE pin OE bit STo0 - 31
0 1 1 Enable
1 0 1 Enable
1 1 1 Enable
0 0 X High impedance state
X X 0 Per-channel high impedance
2 - 0
DR2-0
Data Rate Select.
Input/Output data rate selection. See next table (Table 6) for
detailed programming.
DR2
DR1
DR0
Serial Interface Mode
CLK
(CPLL=0)
CLK
(CPLL=1)
0
0
0
8 Mbps
16.384 MHz
16.384 MHz
0
0
1
16 Mbps
0
1
0
4 and 8 Mbps
0
1
1
16 and 8 Mbps
1
0
0
4 Mbps
16.384 MHz
8.192 MHz
1
0
1
2 and 4 Mbps
1
1
0
2 Mbps
16.384 MHz
8.192 MHz
Table 6 - Serial Data Rate Selections and External Clock Rates
Bit
Name
Description
Table 5 - Control Register Bits (continued)
Read/Write Address:
Reset Value:
0000
H
,
0000
H
.
7
6
5
4
3
2
1
0
8
9
10
11
12
13
DR0
DR1
BPE
14
15
SFE
0
OSB
MBP
MS
SBER
BPD2
BPD1
BPD0
CBER
0
DR2
CPLL
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