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參數(shù)資料
| 型號： | MT90826AV |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 路由/交換 |
| 英文描述： | Quad Digital Switch |
| 中文描述： | TELECOM, DIGITAL TIME SWITCH, PBGA144 |
| 封裝： | 13 X 13 MM, 1.25 MM HEIGHT, MO-192, LBGA-144 |
| 文件頁數(shù)： | 28/46頁 |
| 文件大?。?/td> | 571K |
| 代理商： | MT90826AV |
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MT90826
Data Sheet
28
Zarlink Semiconductor Inc.
Figure 7 - Examples for Frame Output Offset Timing
The correct data memory content will be presented to the data bus (D0-D15) on the second read cycle.
Bit
Name
Description
12 - 8
BSA4 - BSA0
BER Input Stream Address Bits.
The number expressed in binary notation on
these bits refers to the input data stream which receives the pseudo random
pattern.
7 - 0
BCA7 - BCA0
BER Input Channel Address Bits.
The number expressed in binary notation
on these bits refers to the input channel which receives the pseudo random
pattern.
Table 12 - Bit Error Input Selection (BISR) Register Bits
Bit
Name
Description
15 - 0
BER15 - BER0
Bit Error Rate Count Bits.
The number expressed in binary notation on these
bits refers to the bit error counts. The register content can be cleared by
programming the CBER bit in the control register from zero to one.
Table 13 - Bit Error Count (BECR) Register Bits
F0i
CLK
STo Stream
STo Stream
offset=00, (0ns)
offset=01, (-15ns)
Bit 7
Bit 7
denotes the starting point of the bit cell
(16.384MHz)
Read/Write Address:
Reset value:
0011
H
for BISR register,
0000
H
7
6
5
4
3
2
1
0
8
9
10
11
12
13
BCA0
BCA1
BCA2
BCA3
14
15
BCA4
BCA5
BCA6
BCA7
BSA0
BSA1
BSA2
BSA3
BSA4
0
0
0
Read Address:
0012
H
for BECR register,
7
6
5
4
3
2
1
0
8
9
10
11
12
13
14
15
BER0
BER1
BER2
BER3
BER4
BER5
BER6
BER7
BER8
BER9
BER10
BER11
BER12
BER13
BER14
BER15
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