參數(shù)資料
型號(hào)： MT90826AV
廠商： ZARLINK SEMICONDUCTOR INC
元件分類： 路由/交換
英文描述： Quad Digital Switch
中文描述： TELECOM, DIGITAL TIME SWITCH, PBGA144
封裝： 13 X 13 MM, 1.25 MM HEIGHT, MO-192, LBGA-144
文件頁數(shù)： 19/46頁
文件大?。?/td> 571K
代理商： MT90826AV
MT90826
Data Sheet
19
Zarlink Semiconductor Inc.
Bit
Name
Description
15 - 13
BPD2-0
Block Programming Data.
These bits carry the value to be loaded into the
connection memory block whenever the memory block programming feature is
activated. After the MBP bit is set to 1 and the BPE bit is set to 1, the contents of the
bits BPD2- 0 are loaded into bit 15 to bit 13 of the connection memory. Bit 12 to bit 0 of
the connection memory are set to 0.
12
Unused
Must be zero for normal operation
.
11
CPLL
PLL Input Frequency Select.
When zero or one, the CLK input is 16.384 MHz and
the F0i input is 60 ns wide. When one, the CLK input is 8.192 MHz and the F0i input is
122 ns wide. See Table 6 for the usage of the clock frequency.
10
CBER
Clear Bit Error Rate Register
. A zero to one transition in this bit resets the internal
bit error counter and the bit error count register to zero.
9
SBER
Start Bit Error Rate Test
. A zero to one transition in this bit starts the bit error rate
test. The bit error test result is kept in the bit error count register. A one to zero
transition stops the bit error rate test and the internal bit error counter.
8
SFE
Start Frame Evaluation.
A zero to one transition in this bit starts the frame evaluation
procedure. When the CFE bit in the frame alignement (FAR) register changes from
zero to one, the evaluation procedure stops. To start another frame evaluation cycle,
set this bit to zero.
7
Unused
Must be zero for normal operation.
6
BPE
Begin Block programming Enable.
A zero to one transition of this bit enables the
memory block programming function. The BPE and BPD2-0 bits have to be defined in
the same write operation. Once the BPE bit is set high, the device requires two frames
to complete the block programming. After the programming function has finished, the
BPE bit returns to zero to indicate the operation is completed. When the BPE = 1, the
BPE or MBP can be set to 0 to abort the programming operation.
When BPE = 1, the other bits in the control register must not be changed for two
frames to ensure proper operation.
5
MBP
Memory Block Program.
When 1, the connection memory block programming
feature is ready to program Bit13 to Bit15 of the connection memory. When 0, feature
is disabled.
Table 5 - Control Register Bits
Read/Write Address:
Reset Value:
0000
H
,
0000
H
.
7
6
5
4
3
2
1
0
8
9
10
11
12
13
DR0
DR1
BPE
14
15
SFE
0
OSB
MBP
MS
SBER
BPD2
BPD1
BPD0
CBER
0
DR2
CPLL
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