參數(shù)資料
型號(hào)： MT90826AV
廠商： ZARLINK SEMICONDUCTOR INC
元件分類： 路由/交換
英文描述： Quad Digital Switch
中文描述： TELECOM, DIGITAL TIME SWITCH, PBGA144
封裝： 13 X 13 MM, 1.25 MM HEIGHT, MO-192, LBGA-144
文件頁(yè)數(shù)： 21/46頁(yè)
文件大?。?/td> 571K
代理商： MT90826AV
MT90826
Data Sheet
21
Zarlink Semiconductor Inc.
Bit
Name
Description
15 - 11
FE4-0
Frame Evaluation Input Select.
The binary value expressed in these bits
refers to the frame evaluation inputs, FEi0 to FEi31.
10
CFE
Complete Frame Evaluation.
When CFE = 1, the frame evaluation is
completed and FD9 to FD0 bits contains a valid frame alignment offset.
This bit is reset to zero, when SFE bit in the control register is changed from 1
to 0.
9
FD9
Frame Delay Bit 9.
The falling edge of FEi input is sampled during the internal
master clock high phase (FD9 = 1) or during the low phase (FD9 = 0). This bit
allows the measurement resolution to 1/2 internal master clock cycle.
See Figure 5 for clock signal alignment.
Internal Master Clock Operation Mode
C8i 2 Mbps
C16i 4 Mbps, 2&4 Mbps
C32i 8 Mbps, 16 Mbps, 4&8 Mbps, 16&8 Mbps
8 - 0
FD8-0
Frame Delay Bits.
The binary value expressed in these bits refers to the
measured input offset value. These bits are reset to zero when the SFE bit of
the control register changes from 1 to 0. (FD8 = MSB, FD0 = LSB)
Table 7 - Frame Alignment (FAR) Register Bits
Read/Write Address:
Reset Value:
0001
H
,
0000
H
.
7
6
5
4
3
2
1
0
8
9
10
11
12
13
FD0
FD1
FD2
FD3
FD4
FD5
FD6
FD7
FD8
FD9
CFE
FE0
FE1
FE2
FE3
FE4
14
15
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參數(shù)描述
MT90840 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Distributed Hyperchannel Switch
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