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參數(shù)資料
| 型號(hào)： | MT90221 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | Quad IMA/UNI PHY Device(四端口 IMA/UNI 物理層設(shè)備（四端口ATM IMA和UNI處理器）) |
| 中文描述： | 四IMA的/單向物理層設(shè)備（IMA的四端口/單向物理層設(shè)備（四端口自動(dòng)柜員機(jī)IMA的和單向處理器）） |
| 文件頁(yè)數(shù)： | 81/116頁(yè) |
| 文件大?。?/td> | 309K |
| 代理商： | MT90221 |
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MT90221
73
a. Bit 7 is present only for Link 0. In all other Link Status Registers, this bit is set to 0.
b. Bit 6 is present only for Link 0. In all other Link Status Registers, this bit is set to 0.
Address (Hex):
Direct access
Reset Value (Hex):
222 - 225
1 Status register per link
00
Bit #
7
a
Type
Description
R
A ’1’ in this bit means that at least one of the IRQ sources from the IMA Group Overflow
Status Register is requesting service. This bit can be cleared only by service the source
of the IRQ.
This bit is valid only for the IRQ Link 0 Status register and is reading always a 0 for the
IRQ Link 1-3 Status registers.
A 1 in this bit means that at least one of the Ready bit used to initiate a transfer of a TX
ICP cell for at least 1 of the IMA Group is returned to 1 (meaning that the transfer of the
TX ICP cell is complete) or a frame pulse was detected for an IMA Group. This bit is
cleared by writing a 0 to it.
This bit is valid only for the IRQ Link 0 Status register and is reading always a 0 for the
IRQ Link 1-3 Status registers.
ICP Cell with changes received. The link has received an ICP cell which contain one or
more changes in it. This status bit can be cleared by writing a ’0’ to it. This bit is set when
an ICP Cell buffer as defined in RX ICP Cell type ram register 1 or 2.
IV. The Link has received an ICP cell which contain a violation as defined in Table 16 of
IMA Spec. This status bit can be cleared by writing a ’0’ to it.
LODS. The Link is Out of Delay Synchronization. This status bit can be cleared by writing
a ’0’ to it.
LIF. Loss of IMA Frame. This status bit can be cleared by writing a ’0’ to it.
LCD Loss of Cell Delineation. This status bit can be cleared by writing a ’0’ to it.
Link Counter Overflow Interrupt. One or more counters associated with the link
overflowed. This status bit can be cleared only by reading or writing to the counter(s)
which is (are) the source for the IRQ.
6
b
R/W
5
R/W
4
R/W
3
R/W
2
1
0
R/W
R/W
R
Table 96 - IRQ Link Status Registers
Address (Hex):
Direct access
Reset Value (Hex):
219 - 21C
1 Enable register per link Status reg
00
Bit #
Type
Description
7:0
R/W
Each bit set to ’1’ will enable the generation of the interrupt when the corresponding bit in
the IRQ Link Status register is set.
Table 97 - IRQ Link Enable Registers
Address (Hex):
Direct access
Reset Value (Hex):
235
XD
Bit #
Type
Description
7:4
3:0
R
Reserved.
Each bit set to ’1’ represent an overflow condition from the IMA Group associated with the
bit. There is one bit for each IMA Group. A bit is set when one or more of the 4 counters
or the RX UTOPIA FIFO associated with an IMA Group overflows.
R/W
Table 98 - IRQ IMA Group Overflow Status Register
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| MT9041A | () |
| MT9041B | T1/E1 System Synchronizer(T1/E1系統(tǒng)同步裝置（由一個(gè)數(shù)字鎖相環(huán)組成）) |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT90221AL | 制造商:MITEL 制造商全稱(chēng):Mitel Networks Corporation 功能描述:Quad IMA/UNI PHY Device |
| MT90222 | 制造商:ZARLINK 制造商全稱(chēng):Zarlink Semiconductor Inc 功能描述:4/8/16 Port IMA/TC PHY Device |
| MT90222AG | 制造商:Microsemi Corporation 功能描述:ATM IMA 40MBPS 2.5V 384BGA - Trays |
| MT90222AG2 | 制造商:Microsemi Corporation 功能描述:ATM IMA 40MBPS 2.5V 384BGA /BAKE/DRYPACK - Trays |
| MT90223AG | 制造商:Microsemi Corporation 功能描述:ATM IMA 80MBPS 2.5V 384BGA - Trays |
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