參數(shù)資料
型號： MT90221
廠商： Mitel Networks Corporation
英文描述： Quad IMA/UNI PHY Device(四端口 IMA/UNI 物理層設備（四端口ATM IMA和UNI處理器）)
中文描述： 四IMA的/單向物理層設備（IMA的四端口/單向物理層設備（四端口自動柜員機IMA的和單向處理器））
文件頁數(shù)： 69/116頁
文件大小： 309K
代理商： MT90221
MT90221
61
7.7
RX Delay Registers Description
Tables 65 to 74 describe the
RX Delay
registers.
Address (Hex):
Synchronized access
Reset Value (Bin):
280
1X000000
Bit #
Type
Description
7
R
Upon a write to this register, the bit will go to 0 and will return to 1 when the transfer is
completed
Toggle Bit.
Write 0 to initiate a transfer from the MT90221 registers to the external RAM.
Write 1 to initiate a transfer from the external RAM to the MT90221 registers.
Reserved, write 0 for normal operation.
When Test Mode bit is 1; write 1 to enable the direct addressing mode to the External
SRAM.
When Test Mode bit is 1; write 0 for normal operation.Write 1 for disabling all access to
the external RAM except for the uP port (for RAM test purposes)
When bit 1 is 1, there is no access to the external RAM (no reset or read or write action to
the external RAM is done).
When bit 1 is 0 and bit 0 is 0, then the external RAM is initialized.
When bit 1 is 0 and bit 0 is 1, then a read or write access to the external RAM is
performed, as defined by bit 5.
6
5
R
R/W
4
3
R/W
R/W
2
R/W
1:0
R/W
Table 65 - RX External SRAM Control Register
Address (Hex):
Direct access
281
Used to increment or decrement the recombiner delay for an IMA Group.
The value is in the Guardband/Delta Delay register
00
Reset Value (Hex):
Bit #
Type
Description
7
R/W
Write a 1 to decrement the recombiner delay of IMA Group #3. The bit will return to 0
when the delay is adjusted. Writing a 0 has no effect.
Write a 1 to increment the recombiner delay of IMA Group #3. The bit will return to 0 when
the delay is adjusted. Writing a 0 has no effect.
Write a 1 to decrement the recombiner delay of IMA Group #2. The bit will return to 0
when the delay is adjusted. Writing a 0 has no effect.
Write a 1 to increment the recombiner delay of IMA Group #2. The bit will return to 0 when
the delay is adjusted. Writing a 0 has no effect.
Write a 1 to decrement the recombiner delay of IMA Group #1. The bit will return to 0
when the delay is adjusted. Writing a 0 has no effect.
Write a 1 to increment the recombiner delay of IMA Group #1. The bit will return to 0 when
the delay is adjusted. Writing a 0 has no effect.
Write a 1 to decrement the recombiner delay of IMA Group #0. The bit will return to 0
when the delay is adjusted. Writing a 0 has no effect.
Write a 1 to increment the recombiner delay of IMA Group #0. The bit will return to 0 when
the delay is adjusted. Writing a 0 has no effect.
6
R/W
5
R/W
4
R/W
3
R/W
2
R/W
1
R/W
0
R/W
Table 66 - Increment/Decrement Delay Control Register
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相關代理商/技術(shù)參數(shù)
參數(shù)描述
MT90221AL 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:Quad IMA/UNI PHY Device
MT90222 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:4/8/16 Port IMA/TC PHY Device
MT90222AG 制造商:Microsemi Corporation 功能描述:ATM IMA 40MBPS 2.5V 384BGA - Trays
MT90222AG2 制造商:Microsemi Corporation 功能描述:ATM IMA 40MBPS 2.5V 384BGA /BAKE/DRYPACK - Trays
MT90223AG 制造商:Microsemi Corporation 功能描述:ATM IMA 80MBPS 2.5V 384BGA - Trays
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