參數(shù)資料
型號: MT90221
廠商: Mitel Networks Corporation
英文描述: Quad IMA/UNI PHY Device(四端口 IMA/UNI 物理層設(shè)備(四端口ATM IMA和UNI處理器))
中文描述: 四IMA的/單向物理層設(shè)備(IMA的四端口/單向物理層設(shè)備(四端口自動柜員機(jī)IMA的和單向處理器))
文件頁數(shù): 53/116頁
文件大小: 309K
代理商: MT90221
MT90221
45
7.2
TX Registers Description
Tables 23 to 37 describe the
Transmit
registers.
Address (Hex):
Direct access
Reset Value (Bin):
140
Used for initialization of the TX Cell RAM (Filler, Idle Cells etc.)
1X000000
Bit #
Type
Description
7
6
5
R
Goes to 0 during initialization and returns to 1 on completion of initialization.
Reserved, write 0 for normal operation.
Reserved. Write 0 for normal operation.
Reserved, write 0’s for normal operation.
Reserved. Write 0 to initialize the Cell RAM.
R/W
R/W
R/W
R/W
4:1
0
Table 23 - TX Cell RAM Control Register
Address (Hex):
Direct access
Reset Value (Hex):
150
00
Bit #
Type
Description
7:4
3:0
W
W
Write 0 for normal operation.
Write 1000 to load the TX Utopia FIFO level of IMA group 0
Write 1001 to load the TX Utopia FIFO level of IMA group 1.
Write 1010 to load the TX Utopia FIFO level of IMA group 2.
Write 1011 to load the TX Utopia FIFO level of IMA group 3.
7:5
4:0
R
R
Reserved, read 0’s.
Level of selected FIFO.
Table 24 - TX UTOPIA FIFO Level Register
Address (Hex):
Direct access
Reset Value (Hex):
14A
33
Bit #
Type
Description
7:4
3:0
R/W
R/W
TX FIFO Length Link 1.
TX FIFO Length Link 0.
Table 25 - TX FIFO Length Definition Register 1
Address (Hex):
Direct access
Reset Value (Hex):
14B
33
Bit #
Type
Description
7:4
3:0
R/W
R/W
TX FIFO Length Link 3.
TX FIFO Length Link 2.
Table 26 - TX FIFO Length Definition Register 2
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