參數(shù)資料
型號(hào): MT90221
廠商: Mitel Networks Corporation
英文描述: Quad IMA/UNI PHY Device(四端口 IMA/UNI 物理層設(shè)備(四端口ATM IMA和UNI處理器))
中文描述: 四IMA的/單向物理層設(shè)備(IMA的四端口/單向物理層設(shè)備(四端口自動(dòng)柜員機(jī)IMA的和單向處理器))
文件頁數(shù): 51/116頁
文件大小: 309K
代理商: MT90221
MT90221
43
Address (Hex):
Direct access
048 - 04B
1 reg. per IMA Group.link. The RxClk signal must be active for correct register
operation
00
Reset Value (Hex):
Bit #
Type
Description
7:5
4:0
R
Unused. Read all 0’s.
UTOPIA PHY Address of IMA Group N.
R/W
Table 18 - UTOPIA Output Group Address Registers
Address (Hex):
Direct access
04C
1 register to enable the links in UNI mode. The RxClk signal must be active for
correct register operation
00
Reset Value (Hex):
Bit #
Type
Description
7-4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
Reserved. Write 0 for normal operation.
Enable UTOPIA PHY address of link 3. A 1 enables the PHY port Address. UNI mode
Enable UTOPIA PHY address of link 2. A 1 enables the PHY port Address. UNI mode
Enable UTOPIA PHY address of link 1. A 1 enables the PHY port Address. UNI mode
Enable UTOPIA PHY address of link 0. A 1 enables the PHY port Address. UNI mode
Table 19 - UTOPIA Output Link PHY Enable Register
Address (Hex):
Direct access
04D
1 register to enable the IMA Groups. The RxClk signal must be active for correct
register operation
X0000000
Reset Value (Bin):
Bit #
Type
Description
7
R
Watch clock. This bit reflects the level present on the RX UTOPIA Clock pin when this
register is read.
Reserved, write 0 for normal operation.
Reset UTOPIA RX state machines when set to 1.
Reserved, write ’0’ for normal operation.
Enable UTOPIA PHY address of IMA Group 3. A 1 enables the PHY port Address.
Enable UTOPIA PHY address of IMA Group 2. A 1 enables the PHY port Address.
Enable UTOPIA PHY address of IMA Group 1. A 1 enables the PHY port Address.
Enable UTOPIA PHY address of IMA Group 0. A 1 enables the PHY port Address.
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Table 20 - UTOPIA Output Group PHY Enable Register
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