參數(shù)資料
型號(hào)： MT58L512Y32D
廠商： Micron Technology, Inc.
英文描述： 16Mb SYNCBURST⑩ SRAM
中文描述： ⑩的SRAM 16Mb的SYNCBURST
文件頁(yè)數(shù)： 9/34頁(yè)
文件大?。?/td> 526K
代理商： MT58L512Y32D
9
16Mb: 1 Meg x 18, 512K x 32/36 Pipelined, DCD SyncBurst SRAM
MT58L1MY18D_2.p65 – Rev 7/00
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2000, Micron Technology, Inc.
16Mb: 1 MEG x 18, 512K x 32/36
PIPELINED, DCD SYNCBURST SRAM
ADVANCE
FBGA PIN DESCRIPTIONS (continued)
x18
9A
x32/x36
9A
SY MBOL
ADV#
TY PE
Input
DESCRIPTION
Synchronous Address Advance: This active LOW input is used to
advance the internal burst counter, controlling burst access after the
external address is loaded. A HIGH on ADV# effectively causes wait
states to be generated (no address advance). To ensure use of
correct address during a WRITE cycle, ADV# must be HIGH at the
rising edge of the first clock after an ADSP# cycle is initiated.
Synchronous Address Status Processor: This active LOW input
interrupts any ongoing burst, causing a new external address to be
registered. A READ is performed using the new address,
independent of the byte write enables and ADSC#, but dependent
upon CE#, CE2, and CE2#. ADSP# is ignored if CE# is HIGH. Power-
down state is entered if CE2 is LOW or CE2# is HIGH.
Synchronous Address Status Controller: This active LOW input
interrupts any ongoing burst, causing a new external address to be
registered. A READ or WRITE is performed using the new address if
CE# is LOW. ADSC# is also used to place the chip into power-down
state when CE# is HIGH.
Mode: This input selects the burst sequence. A LOW on this
input selects “l(fā)inear burst.” NC or HIGH on this input selects
“interleaved burst.” Do not alter input state while device is
operating.
Input/ SRAM Data I/Os: For the x18 version, Byte “a” is associated DQas;
Output Byte “b” is associated with DQbs. For the x32 and x36 versions,
Byte “a” is associated with DQas; Byte “b” is associated with DQbs;
Byte “c” is associated with DQcs; Byte “d” is associated with DQds.
Input data must meet setup and hold times around the rising edge
of CLK.
9B
9B
ADSP#
Input
8A
8A
ADSC#
Input
1R
1R
MODE
(LB0#)
Input
(a)
10J, 10K,
10L, 10M, 11D, 10L, 10M, 11J,
11E, 11F, 11G 11K, 11L, 11M
(b)
1J, 1K,
1L, 1M, 2D,
2E, 2F, 2G
(a)
10J, 10K,
DQa
(b)
10D, 10E,
10F, 10G, 11D,
11E, 11F, 11G
(c)
1D, 1E,
1F, 1G, 2D,
2E, 2F, 2G
(d)
1J, 1K, 1L,
1M, 2J, 2K,
2L, 2M
11N
11C
1C
1N
DQb
DQc
DQd
11C
1N
–
–
NC/
DQPa
NC/
DQPb
NC/
DQPc
NC/
DQPd
V
DD
NC/
I/O
No Connect/Parity Data I/Os: On the x32 version, these are No
Connect (NC). On the x18 version, Byte “a” parity is DQPa; Byte “b”
parity is DQPb. On the x36 version, Byte “a” parity is DQPa; Byte
“b” parity is DQPb; Byte “c” parity is DQPc; Byte “d” parity is DQPd.
Supply Power Supply:
See DC Electrical Characteristics and Operating
Conditions for range.
1H, 4D, 4E, 4F, 1H, 4D, 4E, 4F,
4G, 4H, 4J,
4K, 4L, 4M,
8D, 8E, 8F,
8G, 8H, 8J,
8K, 8L, 8M
4G, 4H, 4J,
4K, 4L, 4M,
8D, 8E, 8F,
8G, 8H, 8J,
8K, 8L, 8M
(continued on next page)
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