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參數(shù)資料
| 型號(hào)： | MT58L512Y32D |
| 廠商： | Micron Technology, Inc. |
| 英文描述： | 16Mb SYNCBURST⑩ SRAM |
| 中文描述： | ⑩的SRAM 16Mb的SYNCBURST |
| 文件頁數(shù)： | 24/34頁 |
| 文件大?。?/td> | 526K |
| 代理商： | MT58L512Y32D |
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16Mb: 1 Meg x 18, 512K x 32/36 Pipelined, DCD SyncBurst SRAM
MT58L1MY18D_2.p65 – Rev 7/00
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2000, Micron Technology, Inc.
16Mb: 1 MEG x 18, 512K x 32/36
PIPELINED, DCD SYNCBURST SRAM
ADVANCE
TEST DATA-OUT (TDO)
The TDO output pin is used to serially clock data-out
from the registers. The output is active depending upon
the current state of the TAP state machine. (See Figure 5.)
The output changes on the falling edge of TCK. TDO is
connected to the least significant bit (LSB) of any regis-
ter. (See Figure 6.)
PERFORMING A TAP RESET
A RESET is performed by forcing TMS HIGH (V
DD
) for
five rising edges of TCK. This RESET does not affect the
operation of the SRAM and may be performed while the
SRAM is operating.
At power-up, the TAP is reset internally to ensure that
TDO comes up in a High-Z state.
TAP REGISTERS
Registers are connected between the TDI and TDO
pins and allow data to be scanned into and out of the
SRAM test circuitry. Only one register can be selected at
a time through the instruction register. Data is serially
loaded into the TDI pin on the rising edge of TCK. Data
is output on the TDO pin on the falling edge of TCK.
INSTRUCTION REGISTER
Three-bit instructions can be serially loaded into the
instruction register. This register is loaded when it is
placed between the TDI and TDO pins as shown in
Figure 5. Upon power-up, the instruction register is
loaded with the IDCODE instruction. It is also loaded
with the IDCODE instruction if the controller is placed
in a reset state as described in the previous section.
When the TAP controller is in the Capture-IR state,
the two least significant bits are loaded with a binary
“01” pattern to allow for fault isolation of the board-
level serial test data path.
BY PASS REGISTER
To save time when serially shifting data through
registers, it is sometimes advantageous to skip certain
chips. The bypass register is a single-bit register that can
be placed between the TDI and TDO pins. This allows
data to be shifted through the SRAM with minimal
delay. The bypass register is set LOW (V
SS
) when the
BYPASS instruction is executed.
BOUNDARY SCAN REGISTER
The boundary scan register is connected to all the
input and bidirectional pins on the SRAM. Several no
connect (NC) pins are also included in the scan register
to reserve pins for 9Mb and 18Mb Claymore SRAMs. The
x36 configuration has a 68-bit-long register, and the x18
configuration has a 49-bit-long register.
The boundary scan register is loaded with the con-
tents of the RAM I/O ring when the TAP controller is in
the Capture-DR state and is then placed between the TDI
and TDO pins when the controller is moved to the Shift-
DR state. The EX TEST, SAMPLE/PRELOAD and SAMPLE
Z instructions can be used to capture the contents of the
I/O ring.
The Boundary Scan Order tables show the order in
which the bits are connected. Each bit corresponds to
one of the bumps on the SRAM package. The MSB of the
Bypass Register
0
Instruction Register
0
1
2
Identification Register
0
1
2
29
30
31
.
.
.
Boundary Scan Register*
0
1
2
.
.
x
.
.
.
Selection
Circuitry
Selection
Circuitry
TCK
TMS
TAP CONTROLLER
TDI
TDO
*x = 49 for the x18 configuration, x = 68 for the x36 configuration.
Figure 6
TAP Controller Block Diagram
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT58L64L18F | 64K x 18, 3.3V I/O, Flow-Through SyncBurst SRAM(1Mb,3.3V輸入/輸出,流通式同步脈沖靜態(tài)RAM) |
| MT58L32L32F | 32K x 32， 3.3V I/O, Flow-Through SyncBurst SRAM(1Mb,3.3V輸入/輸出,流通式同步脈沖靜態(tài)RAM) |
| MT58L32L36F | 32K x 36， 3.3V I/O, Flow-Through SyncBurst SRAM(1Mb,3.3V輸入/輸出，流通式同步脈沖靜態(tài)RAM) |
| MT58L64L18P | 64K x 18, 3.3V I/O, Pipelined, SCD SyncBurst SRAM(1Mb,3.3V輸入/輸出，流水線式，單循環(huán)取消選擇，同步脈沖靜態(tài)存儲(chǔ)器) |
| MT58L32L32P | 32K x 32, 3.3V I/O, Pipelined, SCD SyncBurst SRAM(1Mb,3.3V輸入/輸出，流水線式，單循環(huán)取消選擇，同步脈沖靜態(tài)存儲(chǔ)器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT58L512Y32DT-10 | 制造商:Cypress Semiconductor 功能描述:512KX32 SRAM PLASTIC TQFP 3.3V 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MT58L512Y32DT-10 ES | 制造商:Cypress Semiconductor 功能描述:512KX32 SRAM PLASTIC TQFP 3.3V |
| MT58L512Y32DT-6 | 制造商:Cypress Semiconductor 功能描述:DS2KX32 SRAM PLASTIC TQFP 3.3V 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MT58L512Y32PT-10 IT | 制造商:Cypress Semiconductor 功能描述:16MB 512KX32 SRAM PLASTIC IND |
| MT58L512Y32PT-6 | 制造商:Cypress Semiconductor 功能描述:512KX32 SRAM PLASTIC TQFP 3.3V |
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