- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄299522 > MT47H64M8CF-5EAT:F DDR DRAM, PBGA60 PDF資料下載
參數(shù)資料
| 型號(hào)： | MT47H64M8CF-5EAT:F |
| 元件分類(lèi)： | DRAM |
| 英文描述： | DDR DRAM, PBGA60 |
| 封裝： | 8 X 10 MM, ROHS COMPLIANT, FBGA-60 |
| 文件頁(yè)數(shù)： | 113/139頁(yè) |
| 文件大小： | 9398K |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)當(dāng)前第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)
5. An n is the most significant address bit for a given density and configuration. Some larg-
er address bits may be “Don’t Care” during column addressing, depending on density
and configuration.
6. Bank addresses (BA) determine which bank is to be operated upon. BA during a LOAD
MODE command selects which mode register is programmed.
7. SELF REFRESH exit is asynchronous.
8. Burst reads or writes at BL = 4 cannot be terminated or interrupted. See Figure 51
(page 102) and Figure 63 (page 113) for other restrictions and details.
9. The power-down mode does not perform any REFRESH operations. The duration of power-
down is limited by the refresh requirements outlined in the AC parametric section.
Table 37: Truth Table – Current State Bank n – Command to Bank n
Notes: 1–6 apply to the entire table
Current
State
CS#
RAS#
CAS#
WE#
Command/Action
Notes
Any
H
X
DESELECT (NOP/continue previous operation)
L
H
NO OPERATION (NOP/continue previous operation)
Idle
L
H
ACTIVATE (select and activate row)
L
H
REFRESH
L
LOAD MODE
Row active
L
H
L
H
READ (select column and start READ burst)
L
H
L
WRITE (select column and start WRITE burst)
L
H
L
PRECHARGE (deactivate row in bank or banks)
Read (auto
precharge
disabled)
L
H
L
H
READ (select column and start new READ burst)
L
H
L
WRITE (select column and start WRITE burst)
L
H
L
PRECHARGE (start PRECHARGE)
Write
(auto pre-
charge disa-
bled)
L
H
L
H
READ (select column and start READ burst)
L
H
L
WRITE (select column and start new WRITE burst)
L
H
L
PRECHARGE (start PRECHARGE)
Notes: 1. This table applies when CKEn - 1 was HIGH and CKEn is HIGH and after tXSNR has been
met (if the previous state was self refresh).
2. This table is bank-specific, except where noted (the current state is for a specific bank
and the commands shown are those allowed to be issued to that bank when in that
state). Exceptions are covered in the notes below.
3. Current state definitions:
Idle:
The bank has been precharged, tRP has been met, and any READ burst is com-
plete.
Row
active:
A row in the bank has been activated, and tRCD has been met. No data bursts/
accesses and no register accesses are in progress.
Read:
A READ burst has been initiated, with auto precharge disabled and has not
yet terminated.
Write: A WRITE burst has been initiated with auto precharge disabled and has not
yet terminated.
512Mb: x4, x8, x16 DDR2 SDRAM
Commands
PDF: 09005aef82f1e6e2
Rev. M 9/08 EN
75
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2004 Micron Technology, Inc. All rights reserved.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT48H16M16LFBF-10IT | 16M X 16 SYNCHRONOUS DRAM, 7 ns, PBGA54 |
| MT48LC8M16A2BB-6ALIT:G | 8M X 16 SYNCHRONOUS DRAM, 5.4 ns, PBGA60 |
| MT49H8M36HU-33 | 8M X 36 DDR DRAM, 0.3 ns, PBGA144 |
| MT4C1024DJ-6L | 1M X 1 FAST PAGE DRAM, 60 ns, PDSO20 |
| MT4C2M8A1DJ-7STR | 2M X 8 FAST PAGE DRAM, 70 ns, PDSO28 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。