8
512Mb: x4, x8, x16 DDR SDRAM
512Mx4x8x16DDR_A.p65
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Rev. A; Pub 10/00
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2000, Micron Technology, Inc.
512Mb: x4, x8, x16
DDR SDRAM
ADVANCE
PIN DESCRIPTIONS (continued)
TSOP PIN NUMBERS
2, 5, 8, 11, 56, 59, 62, 65
5, 11, 56, 62
51
16, 51
SYMBOL
DQ0-7
DQ0-3
DQS
LDQS, UDQS
TYPE
I/O
I/O
I/O
DESCRIPTION
RESERVED NC PINS
1
TSOP PIN NUMBERS
17
SY MBOL
A13
TY PE
I
DESCRIPTION
Address input for 1Gb devices.
NOTE:
1. NC pins not listed may also be reserved for other uses now or in the future. This table simply defines specific NC pins
deemed to be of importance.
Data Input/Output: Data bus for x8 (2, 8, 59 and 65 are NC for x4).
Data Input/Output: Data bus for x4.
Data Strobe: Output with read data, input with write data. DQS is
edge-aligned with read data, centered in write data. It is used to
capture data. For the x16 , LDQS is DQS for DQ0-DQ7 and UDQS is
DQS for DQ8-DQ15. Pin 16 is NC on x4 and x8.
Do Not Use: Must float to minimize noise.
DQ Power Supply: +2.5V ±0.2V. Isolated on the die for improved
noise immunity.
DQ Ground. Isolated on the die for improved noise immunity.
Power Supply: +2.5V ±0.2V.
Ground.
SSTL_2 reference voltage.
No Connect: These pins should be left unconnected.
50
DNU
V
DD
Q
–
3, 9, 15, 55, 61
Supply
6, 12, 52, 58, 64
1, 18, 33
34, 48, 66
49
14, 17, 19, 25, 43, 53
V
SS
Q
V
DD
V
SS
V
REF
NC
Supply
Supply
Supply
Supply
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