參數(shù)資料
型號: MT46V64M8
廠商: Micron Technology, Inc.
英文描述: 16 Meg x 8 x 4 banks DDR SDRAM(16M x 8 x 4組,雙數(shù)據(jù)速率同步動態(tài)RAM)
中文描述: 16梅格× 8 × 4銀行DDR SDRAM內存(1,600 × 8 × 4組,雙數(shù)據(jù)速率同步動態(tài)RAM)的
文件頁數(shù): 56/70頁
文件大?。?/td> 2524K
代理商: MT46V64M8
56
512Mb: x4, x8, x16 DDR SDRAM
512Mx4x8x16DDR_A.p65
Rev. A; Pub 10/00
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2000, Micron Technology, Inc.
512Mb: x4, x8, x16
DDR SDRAM
ADVANCE
Figure 27
x4, x8 Data Output Timing –
t
DQSQ,
t
QH and Data Valid Window
DQ (Last data valid)
DQ
2
DQ
2
DQ
2
DQ
2
DQ
2
DQ
2
DQS
1
DQ (Last data valid)
DQ (First data no longer valid)
DQ (First data no longer valid)
All DQs and DQS, collectively
6
NOTE:
1. DQs transitioning after DQS transition define tDQSQ window. DQS transitions at T2 and at T2n are an
early DQS,
at T3 is a
nominal DQS,
and at T3n is a "late DQS"
2. For a x4, only two DQs apply.
3. tDQSQ is derived at each DQS clock edge and is not cumulative over time and begins with DQS transition and
ends with the last valid transition of DQs .
4. tQH is derived from tHP : tQH = tHP - tQHS.
5. tHP is the lesser of tCL or tCH clock transition collectively when a bank is active.
6. The data valid window is derived for each DQS transitions and is defined as tQH minus tDQSQ.
Earliest signal transition
Latest signal transition
T2
T2
T2
T2n
T2n
T2n
T3
T3
T3
T3n
T3n
T3n
CK
CK#
T1
T2
T3
T4
T2n
T3n
tQH
4
tHP
5
tHP
5
tHP
5
tQH
4
tQH
4
tHP
5
tHP
5
tHP
5
tQH
4
tDQSQ
3
tDQSQ
3
tDQSQ
3
tDQSQ
3
Data
Valid
window
Data
Valid
window
Data
Valid
window
Data
Valid
window
QFC#
相關PDF資料
PDF描述
MT48LC16M8A1TG SYNCHRONOUS DRAM
MT48LC32M4A1 ECONOLINE: RSZ/P - 1kVDC
MT48LC32M4A2 SYNCHRONOUS DRAM
MT48LC32M4A1TG SYNCHRONOUS DRAM
MT48LC8M16A1TG SYNCHRONOUS DRAM
相關代理商/技術參數(shù)
參數(shù)描述