參數(shù)資料
型號(hào)： MT46V64M8
廠商： Micron Technology, Inc.
英文描述： 16 Meg x 8 x 4 banks DDR SDRAM(16M x 8 x 4組,雙數(shù)據(jù)速率同步動(dòng)態(tài)RAM)
中文描述： 16梅格× 8 × 4銀行DDR SDRAM內(nèi)存（1,600 × 8 × 4組，雙數(shù)據(jù)速率同步動(dòng)態(tài)RAM）的
文件頁(yè)數(shù)： 31/70頁(yè)
文件大?。?/td> 2524K
代理商： MT46V64M8
31
512Mb: x4, x8, x16 DDR SDRAM
512Mx4x8x16DDR_A.p65
–
Rev. A; Pub 10/00
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2000, Micron Technology, Inc.
512Mb: x4, x8, x16
DDR SDRAM
ADVANCE
Figure 19
WRITE to READ – Uninterrupting
t
DQSS (NOM)
CK
CK#
COMMAND
WRITE
NOP
NOP
READ
NOP
NOP
ADDRESS
Bank
a
,
Col
b
Bank
a
,
Col
n
NOP
T0
T1
T2
T3
T2n
T4
T5
NOTE
: 1. DI
b
= data-in for column
b
.
2. Three subsequent elements of data-in are applied in the programmed order following DI
b
.
3. An uninterrupted burst of 4 is shown.
4.tWTR is referenced from the first positive CK edge after the last data-in pair.
5. The READ and WRITE commands are to the same bank. However, the READ and WRITE commands may be
to different devices, in which case tWTR is not required and the READ command could be applied earlier.
6. A10 is LOW with the WRITE command (auto precharge is disabled).
T1n
T6
T6n
t
WTR
CL = 2
DQ
DQS
DM
DI
b
DI
n
t
DQSS
t
DQSS (MIN)
CL = 2
DQ
DQS
DM
DI
b
DI
n
t
DQSS
t
DQSS (MAX)
CL = 2
DQ
DQS
DM
DI
b
DI
n
t
DQSS
DON
’
T CARE
TRANSITIONING DATA
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