參數(shù)資料
型號： MT46V64M8
廠商： Micron Technology, Inc.
英文描述： 16 Meg x 8 x 4 banks DDR SDRAM(16M x 8 x 4組,雙數(shù)據(jù)速率同步動(dòng)態(tài)RAM)
中文描述： 16梅格× 8 × 4銀行DDR SDRAM內(nèi)存（1,600 × 8 × 4組，雙數(shù)據(jù)速率同步動(dòng)態(tài)RAM）的
文件頁數(shù)： 62/70頁
文件大小： 2524K
代理商： MT46V64M8
62
512Mb: x4, x8, x16 DDR SDRAM
512Mx4x8x16DDR_A.p65
–
Rev. A; Pub 10/00
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2000, Micron Technology, Inc.
512Mb: x4, x8, x16
DDR SDRAM
ADVANCE
AUTO REFRESH MODE
TIMING PARAMETERS
-7
-75
-8
SYMBOL
t
CH
t
CL
t
CK (2.5)
t
CK (2)
MIN
0.45
0.45
7
7.5
MAX
0.55
0.55
12
12
MIN
0.45
0.45
7.5
10
MAX
0.55
0.55
12
12
MIN
0.45
0.45
8
10
MAX
0.55
0.55
12
12
UNITS
t
CK
t
CK
ns
ns
-7
-75
-8
SYMBOL
t
IH
t
IS
t
RFC
t
RP
MIN
1
1
67
15
MAX
MIN
1
1
75
20
MAX
MIN
1.1
1.1
80
20
MAX
UNITS
ns
ns
ns
ns
CK
CK#
COMMAND
1
NOP2
VALID
VALID
NOP 2
NOP2
PRE
CKE
RA
A0-A9,
A11, A12
1
A10
1
BA0, BA1
1
Bank(s)3
BA
NOTE
: 1. PRE = PRECHARGE, ACT = ACTIVE, AR = AUTO REFRESH, RA = Row Address, BA = Bank Address.
2. NOP commands are shown for ease of illustration; other valid commands may be possible at these times.
CKE must be active during clock positive transitions.
3.
“
Don
’
t Care
”
if A10 is HIGH at this point; A10 must be HIGH if more than one bank is active (i.e.,
must precharge all active banks).
4. DM, DQ, and DQS signals are all
“
Don
’
t Care
”
/High-Z for operations shown.
5. The second AUTO REFRESH is not required and is only shown as an example of two back-to-back
AUTO REFRESH commands.
AR
NOP2
AR5
NOP2
ACT
NOP2
ONE BANK
ALL BANKS
t
CK
t
CH
t
CL
t
IS
t
IS
t
IH
t
IH
t
IS
t
IH
RA
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DQ
4
DM
4
DQS
4
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tRFC
5
tRP
tRFC
T0
T1
T2
T3
T4
Ta0
Tb0
Ta1
Tb1
Tb2
DON
’
T CARE
(
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)(
)
(
)
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