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參數(shù)資料
| 型號： | MT2VDDT832UY-75XX |
| 元件分類： | DRAM |
| 英文描述： | 8M X 32 DDR DRAM MODULE, 0.75 ns, DMA100 |
| 封裝： | LEAD FREE, DIMM-100 |
| 文件頁數(shù)： | 3/27頁 |
| 文件大?。?/td> | 420K |
| 代理商： | MT2VDDT832UY-75XX |
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32MB, 64MB (x32, SR)
100-PIN DDR UDIMM
pdf: 09005aef808ebdbc, source: 09005aef808e914b
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DD2C8_16x32UG.fm - Rev. D 9/04 EN
11
2004 Micron Technology, Inc. All rights reserved.
Commands
Table 8, Commands Truth Table, and Table 9, DM
Operation Truth Table, provide a general reference of
available commands. For a more detailed description
of commands and operations, refer to the 128Mb or
256Mb DDR SDRAM component data sheet.
NOTE:
1. DESELECT and NOP are functionally interchangeable.
2. BA0–BA1 provide device bank address and A0–A11 (32MB) or A0–A12 (64MB) provide row address.
3. BA0–BA1 provide device bank address; A0–A8 provide column address; A10 HIGH enables the auto precharge feature
(nonpersistent), and A10 LOW disables the auto precharge feature.
4. Applies only to read bursts with auto precharge disabled; this command is undefined (and should not be used) for READ
bursts with auto precharge enabled and for WRITE bursts.
5. A10 LOW: BA0–BA1 determine which device bank is precharged. A10 HIGH: all device banks are precharged and BA0–
BA1 are “Don’t Care.”
6. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
7. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE.
8. BA0–BA1 select either the mode register or the extended mode register (BA0 = 0, BA1 = 0 select the mode register; BA0
= 1, BA1 = 0 select extended mode register; other combinations of BA0–BA1 are reserved). A0–A11 (32MB) or A0–A12
(64MB) provide the op-code to be written to the selected mode register.
Table 8:
Commands Truth Table
CKE is HIGH for all commands shown except SELF REFRESH; all states and sequences not shown are illegal or reserved
NAME (FUNCTION)
CS#
RAS#
CAS#
WE#
ADDR
NOTES
DESELECT (NOP)
H
XXX
X
1
NO OPERATION (NOP)
L
HHH
X
1
ACTIVE (Select bank and activate row)
L
H
Bank/Row
2
READ (Select bank and column, and start READ burst)
LH
Bank/Col
3
WRITE (Select bank and column, and start WRITE burst)
L
H
L
Bank/Col
3
BURST TERMINATE
LH
H
L
X
4
PRECHARGE (Deactivate row in bank or banks)
L
H
L
Code
5
AUTO REFRESH or SELF REFRESH (Enter self refresh mode)
LLL
H
X
6, 7
LOAD MODE REGISTER
LLLL
Op-Code
8
Table 9:
DM Operation Truth Table
Used to mask write data; provided coincident with the corresponding data
NAME (FUNCTION)
DM
DQS
WRITE Enable
L
Valid
WRITE Inhibit
HX
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