參數(shù)資料
型號： MT2VDDT832UY-75XX
元件分類： DRAM
英文描述： 8M X 32 DDR DRAM MODULE, 0.75 ns, DMA100
封裝： LEAD FREE, DIMM-100
文件頁數(shù)： 16/27頁
文件大?。?/td> 420K
代理商： MT2VDDT832UY-75XX
32MB, 64MB (x32, SR)
100-PIN DDR UDIMM
pdf: 09005aef808ebdbc, source: 09005aef808e914b
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DD2C8_16x32UG.fm - Rev. D 9/04 EN
23
2004 Micron Technology, Inc. All rights reserved.
Figure 16: SPD EEPROM Timing Diagram
Table 16:
EEPROM Device Select Code
Most significant bit (b7) is sent first
SELECT CODE
DEVICE TYPE IDENTIFIER
CHIP ENABLE
RW
b7
b6
b5
b4
b3
b2
b1
b0
Memory Area Select Code (two arrays)
1010
SA2
SA1
SA0
RW
Protection Register Select Code
0110
SA2
SA1
SA0
RW
Table 17:
EEPROM Operating Modes
MODE
RW BIT
WC
BYTES
INITIAL SEQUENCE
Current Address Read
1VIH or VIL
1
START, Device Select, RW = ‘1’
Random Address Read
0VIH or VIL
1
START, Device Select, RW = ‘0’, Address
1VIH or VIL
1
reSTART, Device Select, RW = ‘1’
Sequential Read
1VIH or VIL
≥ 1
Similar to Current or Random Address Read
Byte Write
0VIL
1
START, Device Select, RW = ‘0’
Page Write
0VIL
≤ 16
START, Device Select, RW = ‘0’
SCL
SDA IN
SDA OUT
tLOW
tSU:STA
tHD:STA
tF
tHIGH
tR
tBUF
tDH
tAA
tSU:STO
tSU:DAT
tHD:DAT
UNDEFINED
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