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參數(shù)資料
| 型號： | MT2VDDT832UY-75XX |
| 元件分類： | DRAM |
| 英文描述： | 8M X 32 DDR DRAM MODULE, 0.75 ns, DMA100 |
| 封裝： | LEAD FREE, DIMM-100 |
| 文件頁數(shù)： | 27/27頁 |
| 文件大?。?/td> | 420K |
| 代理商： | MT2VDDT832UY-75XX |
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32MB, 64MB (x32, SR)
100-PIN DDR UDIMM
pdf: 09005aef808ebdbc, source: 09005aef808e914b
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DD2C8_16x32UG.fm - Rev. D 9/04 EN
9
2004 Micron Technology, Inc. All rights reserved.
NOTE:
1. For a burst length of two, A1–A8 select the two-data-
element block; A0 selects the first access within the
block.
2. For a burst length of four, A2–A8 select the four-data-
element block; A0–A1 select the first access within the
block.
3. For a burst length of eight, A3–A8 select the eight-
data-element block; A0–A2 select the first access within
the block.
4. Whenever a boundary of the block is reached within a
given sequence above, the following access wraps
within the block.
Figure 5: CAS Latency Diagram
Operating Mode
The normal operating mode is selected by issuing a
MODE REGISTER SET command with bits A7–A11
(32MB), or A7–A12 (64MB) each set to zero, and bits
A0–A6 set to the desired values. A DLL reset is initiated
by issuing a MODE REGISTER SET command with bits
A7 and A9–A11 (32MB), or A7 and A9–A12 (64MB) each
set to zero, bit A8 set to one, and bits A0–A6 set to the
desired values. Although not required by the Micron
device, JEDEC specifications recommend when a
LOAD MODE REGISTER command is issued to reset
the DLL, it should always be followed by a LOAD
MODE REGISTER command to select normal operat-
ing mode.
All other combinations of values for A7–A11 (32MB)
or A7–A12 (64MB) are reserved for future use and/or
test modes. Test modes and reserved states should not
be used because unknown operation or incompatibil-
ity with future versions may result.
Extended Mode Register
The extended mode register controls functions
beyond those controlled by the mode register; these
additional functions are DLL enable/disable and out-
put drive strength. These functions are controlled via
the bits shown in Figure 6, Extended Mode Register
Definition Diagram. The extended mode register is
programmed via the LOAD MODE REGISTER com-
mand to the mode register (with BA0 = 1 and BA1 = 0)
and will retain the stored information until it is pro-
grammed again or the device loses power.
The
enabling of the DLL should always be followed by a
LOAD MODE REGISTER command to the mode regis-
ter (BA0/BA1 both LOW) to reset the DLL.
Table 6:
Burst Definition Table
BURST
LENGTH
STARTING
COLUMN
ADDRESS
ORDER OF ACCESSES WITHIN
A BURST
TYPE =
SEQUENTIAL
TYPE =
INTERLEAVED
2
A0
00-1
0-1
11-0
1-0
4
A1
A0
0
0-1-2-3
0
1
1-2-3-0
1-0-3-2
1
0
2-3-0-1
1
3-0-1-2
3-2-1-0
8
A2 A1
A0
0
0-1-2-3-4-5-6-7
0
1
1-2-3-4-5-6-7-0
1-0-3-2-5-4-7-6
0
1
0
2-3-4-5-6-7-0-1
2-3-0-1-6-7-4-5
0
1
3-4-5-6-7-0-1-2
3-2-1-0-7-6-5-4
1
0
4-5-6-7-0-1-2-3
1
0
1
5-6-7-0-1-2-3-4
5-4-7-6-1-0-3-2
1
0
6-7-0-1-2-3-4-5
6-7-4-5-2-3-0-1
1
7-0-1-2-3-4-5-6
7-6-5-4-3-2-1-0
Table 7:
CAS Latency (CL) Table
ALLOWABLE OPERATING
CLOCK FREQUENCY (MHZ)
SPEED
CL = 2
CL = 2.5
-6
–
75
≤ f ≤167
-75Z
75
≤ f ≤133
75
≤ f ≤133
-75
–
75
≤ f ≤133
READ
NOP
Burst Length = 4 in the cases shown
Shown with nominal tAC and nominal tDSDQ
CK
CK#
COMMAND
DQ
DQS
CL = 2.5
T0
T1
T2
T2n
T3
T3n
DON’T CARE
TRANSITIONING DATA
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