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參數(shù)資料
| 型號： | MT2VDDT832UY-75XX |
| 元件分類： | DRAM |
| 英文描述： | 8M X 32 DDR DRAM MODULE, 0.75 ns, DMA100 |
| 封裝： | LEAD FREE, DIMM-100 |
| 文件頁數(shù)： | 17/27頁 |
| 文件大?。?/td> | 420K |
| 代理商： | MT2VDDT832UY-75XX |
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32MB, 64MB (x32, SR)
100-PIN DDR UDIMM
pdf: 09005aef808ebdbc, source: 09005aef808e914b
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DD2C8_16x32UG.fm - Rev. D 9/04 EN
24
2004 Micron Technology, Inc. All rights reserved.
NOTE:
1. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL = 1 and the falling or rising
edge of SDA.
2. This parameter is sampled.
3. For a reSTART condition, or following a WRITE cycle.
4. The SPD EEPROM WRITE cycle time (tWRC) is the time from a valid stop condition of a write sequence to the end of
the EEPROM internal erase/program cycle. During the WRITE cycle, the EEPROM bus interface circuit is disabled, SDA
remains HIGH due to pull-up resistor, and the EEPROM does not respond to its slave address.
Table 18:
Serial Presence-Detect EEPROM DC Operating Conditions
All voltages referenced to VSS; VDDSPD = +2.3V to +3.6V
PARAMETER/CONDITION
SYMBOL
MIN
MAX
UNITS
SUPPLY VOLTAGE
VDD
2.3
3.6
V
INPUT HIGH VOLTAGE: Logic 1; All inputs
VIH
VDD x 0.7 VDD + 0.5
V
INPUT LOW VOLTAGE: Logic 0; All inputs
VIL
-1
VDD x 0.3
V
OUTPUT LOW VOLTAGE: IOUT = 3mA
VOL
–0.4
V
INPUT LEAKAGE CURRENT: VIN = GND to VDD
ILI
–10
A
OUTPUT LEAKAGE CURRENT: VOUT = GND to VDD
ILO
–10
A
STANDBY CURRENT: SCL = SDA = VDD - 0.3V; All other inputs = VSS or VREF
ISB
–30
A
POWER SUPPLY CURRENT: SCL clock frequency = 100 KHz
ICC
–2
mA
Table 19:
Serial Presence-Detect EEPROM AC Operating Conditions
All voltages referenced to VSS; VDDSPD = +2.3V to +3.6V
PARAMETER/CONDITION
SYMBOL
MIN
MAX
UNITS
NOTES
SCL LOW to SDA data-out valid
tAA
0.2
0.9
s
1
Time the bus must be free before a new transition can start
tBUF
1.3
s
Data-out hold time
tDH
200
ns
SDA and SCL fall time
tF
300
ns
2
Data-in hold time
tHD:DAT
0
s
Start condition hold time
tHD:STA
0.6
s
Clock HIGH period
tHIGH
0.6
s
Noise suppression time constant at SCL, SDA inputs
tI50
ns
Clock LOW period
tLOW
1.3
s
SDA and SCL rise time
tR0.3
s
2
SCL clock frequency
fSCL
400
KHz
Data-in setup time
tSU:DAT
100
ns
Start condition setup time
tSU:STA
0.6
s
3
Stop condition setup time
tSU:STO
0.6
s
WRITE cycle time
tWRC
10
ms
4
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