參數(shù)資料
型號(hào)： MT2VDDT832UY-75XX
元件分類： DRAM
英文描述： 8M X 32 DDR DRAM MODULE, 0.75 ns, DMA100
封裝： LEAD FREE, DIMM-100
文件頁(yè)數(shù)： 1/27頁(yè)
文件大?。?/td> 420K
代理商： MT2VDDT832UY-75XX
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.
pdf: 09005aef808ebdbc, source: 09005aef808e914b
DD2C8_16x32UG.fm - Rev. D 9/04 EN
1
2004 Micron Technology, Inc. All rights reserved.
32MB, 64MB (x32, SR)
100-PIN DDR UDIMM
DDR SDRAM
UNBUFFERED DIMM
MT2VDDT832U – 32MB
MT2VDDT1632U – 64MB
For the latest data sheet, please refer to the Micron Web
site: www.micron.com/products/modules
Features
100-pin, dual in-line memory module (DIMM)
Fast data transfer rate PC2100 and PC2700
Utilizes 266 MT/s or 333 MT/s DDR SDRAM
components
32MB (8 Meg x 32) and 64MB (16 Meg x 32)
VDD = VDDQ = +2.5V
2.5V I/O (SSTL_2 compatible)
Commands entered on each positive CK edge
DQS edge-aligned with data for READs; center-
aligned with data for WRITEs
Internal, pipelined double data rate (DDR)
architecture; two data accesses per clock cycle
Bidirectional data strobe (DQS) transmitted/
received with data—i.e., source-synchronous data
capture
Differential clock inputs CK and CK#
Four internal device banks for concurrent operation
Programmable burst lengths: 2, 4, or 8
Auto precharge option
Serial Presence Detect (SPD) with EEPROM
Programmable READ CAS latency
Auto Refresh and Self Refresh Modes
15.625s (32MB), 7.8125s (64MB) maximum
average periodic refresh interval
Gold edge contacts
Figure 1:
100-Pin DIMM (MO-161)
NOTE:
1. Contact Micron for product availability.
2. CL = CAS (READ) latency.
OPTIONS
MARKING
Package
100-pin DIMM (standard)
G
100-pin DIMM (lead-free)1
Y
Operating Temperature Range
Commercial (ambient)
none
Industrial (ambient)
I
Frequency/CAS Latency2
6ns/167 MHz (333 MT/s) CL = 2.5
-6
7.5ns/133 MHz (266 MT/s) CL = 2
-75Z1
7.5ns/133 MHz (266 MT/s) CL = 2.5
-75
Table 1:
Address Table
MT2VDDT832U
MT2VDDT1632U
Refresh Count
4K
8K
Row Addressing
4K (A0–A11)
8K (A0–A12)
Device Bank Addressing
4 (BA0, BA1)
Device Configuration
128Mb (8 Meg x 16)
256Mb (16 Meg x 16)
Column Addressing
512 (A0–A8)
Module Rank Addressing
1 (S0#)
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